SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Because the external XO clock input is used as the reference input for the VCO calibration, the XO input amplitude and frequency must be stable before the start of VCO calibration to ensure successful PLL lock and output start-up. If the XO clock is not stable prior to VCO calibration, the VCO calibration can fail and prevent PLL lock and output clock start-up.
If the XO clock has a slow start-up time or has glitches on power-up (due to a slow or non-monotonic power supply ramp, for example), TI recommends to delay the start of VCO calibration until after the XO is stable. This could be achieved by delaying the PDN low-to-high transition until after the XO clock has stabilized using one of the methods described in Power Up From Split-Supply Rails. It is also possible to issue a device soft-reset after the XO clock has stabilized to manually trigger the VCO calibration and PLL start-up sequence.