SNVSBR8D March   2020  – June 2022 LMQ61460

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EN/SYNC Uses for Enable and VIN UVLO
      2. 8.3.2  EN/SYNC Pin Uses for Synchronization
      3. 8.3.3  Adjustable Switching Frequency
      4. 8.3.4  Clock Locking
      5. 8.3.5  PGOOD Output Operation
      6. 8.3.6  Internal LDO, VCC UVLO, and BIAS Input
      7. 8.3.7  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      8. 8.3.8  Adjustable SW Node Slew Rate
      9. 8.3.9  Spread Spectrum
      10. 8.3.10 Soft Start and Recovery From Dropout
      11. 8.3.11 Output Voltage Setting
      12. 8.3.12 Overcurrent and Short Circuit Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  BIAS
        10. 9.2.2.10 CFF and RFF Selection
        11. 9.2.2.11 External UVLO
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5 V.  VIN1 shorted to VIN2 = VIN.  VOUT is converter output voltage.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE AND CURRENT
VIN_OPERATEInput operating voltage(3)Needed to start up3.95V
Once operating3.0
VIN_OPERATE_HHysteresis(3)1V
IQOperating quiescent current (not switching); measured at the VIN pin(1)VFB = +5%, VBIAS = 5 V0.66µA
IBIASCurrent into the BIAS pin (not switching, maximum at TJ = 125°C)(1)VFB = +5%, VBIAS = 5 V, auto mode2431.2µA
ISDShutdown quiescent current; measured at the VIN pinEN = 0 V, TJ = 25℃0.66µA
ENABLE
VENEnable input threshold voltage – rising1.263V
VEN-ACCEnable input threshold voltage – rising deviation from typical–8.1%8.1%
VEN-HYSTEnable threshold hysteresis as percentage of VEN  (typical)24%28%32%
VEN-WAKEEnable wake-up threshold0.4V
IENEnable pin input currentVIN = EN = 13.5 V2.3µA
VEN_SYNCEdge height necessary to sync using the EN/SYNC pinRise and fall time < 30 ns2.4V
LDO - VCC
VCCInternal VCC voltageVBIAS > 3.4 V, CCM operation(3)3.3V
VBIAS = 3.1 V, non-switching3.1
VCC_UVLOInternal VCC input undervoltage lockoutVCC rising undervoltage threshold3.6V
VCC_UVLO_HYSTInternal VCC input undervoltage lockoutHysteresis below VCC_UVLO1.1V
FEEDBACK
VFB_accInitial reference voltage accuracy for 5-V, 3.3-V, and adjustable (1 V FB) versionsVIN = 3.3 V to 36 V, TJ = 25℃, FPWM mode–1%1%
IFBInput current from FB to AGND Adjustable versions only, FB = 1 V10nA
OSCILLATOR
fADJMinimum adjustable frequency by RT or SYNCRT = 66.5 kΩ0.180.20.22MHz
Adjustable frequency by RT or SYNC with 400 kHz settingRT = 33.2 kΩ 0.360.40.44MHz
Maximum adjustable frequency by RT or SYNCRT = 5.76 kΩ1.982.22.42MHz
MOSFETS
RDS(ON)_HSPower switch on-resistanceHigh-side MOSFET RDS(ON)4182mΩ
RDS(ON)_LSPower switch on-resistanceLow-side MOSFET RDS(ON)2145mΩ
VBOOT_UVLOVoltage on CBOOT pin compared to SW, which turns off high-side switch2.1V
CURRENT LIMITS
IL-HSHigh-side switch current limit(2)Duty cycle approaches 0%8.910.311.5A
IL-LSLow-side switch current limit6.17.18.1A
IL-ZCZero-cross current limit. Positive current direction is out of the SW pinAuto mode, static measurement0.25A
IL-NEGNegative current limit FPWM and SYNC modes.  Positive current direction is out of the SW pin.FPWM operation–3A
IPK_MIN_0Minimum peak command in auto mode and device current ratingPulse duration < 100 ns25%
IPK_MIN_100Minimum peak command in auto mode and device current ratingPulse duration > 1 µs12.5%
VHICCUPRatio of FB voltage to in-regulation FB voltageNot during soft start40%
POWER GOOD
PGDOVPGOOD upper threshold – rising% of VOUT setting105%107%110%
PGDUVPGOOD lower threshold - falling% of VOUT setting92%94%96.5%
PGDHYSTPGOOD upper threshold (rising and falling)% of VOUT setting1.3%
VIN(PGD_VALID)Input voltage for proper PGOOD function1.0V
VPGD(LOW) Low level PGOOD function output voltage46-µA pullup to PGOOD pin, VIN = 1.0 V, EN = 0 V0.4V
1-mA pullup to the PGOOD pin, VIN = 13.5 V, EN = 0 V0.4
2-mA pullup to the PGOOD pin, VIN = 13.5 V, EN = 3.3 V0.4
RPGDRDS(ON) of PGOOD output1-mA pullup to PGOOD pin, EN = 0 V1740Ω
1-mA pullup to PGOOD pin, EN = 3.3 V4090Ω
IOVPulldown current at the SW node under overvoltage condition0.5mA
THERMAL SHUTDOWN
TSD_RThermal shutdown rising threshold(3)158168180℃
TSD_HYSTThermal shutdown hysteresis(3)10℃
(1) This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal.  It does not represent the total input current to the system while regulating. For additional information, reference the Systems Characteristics and Section 8.3.14.
(2) High side current limit is a function of duty factor.  High-side current limit value is highest at small duty factor and less at higher duty factors.
(3) Parameter specified by design, statistical analysis and production testing of correlated parameters.