SNVSAH2E December   2015  – August 2020 LMR23630

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency Peak Current Mode Control
      2. 8.3.2  Adjustable Frequency
      3. 8.3.3  Adjustable Output Voltage
      4. 8.3.4  Enable/Sync
      5. 8.3.5  VCC, UVLO
      6. 8.3.6  Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions
      7. 8.3.7  Power Good (PGOOD)
      8. 8.3.8  Internal Compensation and CFF
      9. 8.3.9  Bootstrap Voltage (BOOT)
      10. 8.3.10 Overcurrent and Short-Circuit Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light Load Operation (PFM Version)
      5. 8.4.5 Light Load Operation (FPWM Version)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Output Voltage Setpoint
        3. 9.2.2.3  Switching Frequency
        4. 9.2.2.4  Inductor Selection
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Feed-Forward Capacitor
        7. 9.2.2.7  Input Capacitor Selection
        8. 9.2.2.8  Bootstrap Capacitor Selection
        9. 9.2.2.9  VCC Capacitor Selection
        10. 9.2.2.10 Undervoltage Lockout Setpoint
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Compact Layout for EMI Reduction
    4. 11.4 Ground Plane and Thermal Considerations
    5. 11.5 Feedback Resistors
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDA|8
  • DRR|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 VCC, UVLO

The LMR23630 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal voltage for VCC is 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. Place a high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23630.

VCC undervoltage lockout (UVLO) prevents the LMR23630 from operating until the VCC voltage exceeds 3.3 V (typical). The VCC UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to temporary VIN drops.