SLOS447J September   2004  – June 2025 LMV341 , LMV342 , LMV344

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: V+ = 2.7V
    6. 5.6 Electrical Characteristics: V+ = 5V
    7. 5.7 Shutdown Characteristics: V+ = 2.7V
    8. 5.8 Shutdown Characteristics: V+ = 5V
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PMOS Input Stage
      2. 6.3.2 CMOS Output Stage
      3. 6.3.3 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Thermal Information

THERMAL METRIC(1)LMV342LMV344LMV341LMV342LMV344UNIT
D (SOIC)DBV
(SOT-23)		DCK (SC70)DGK (VSSOP)PW (TSSOP)
8 PINS14 PINS6 PINS6 PINS8 PINS14 PINS
RθJAJunction-to-ambient thermal resistance(2) (3)123.988.7193.4196.8192.3118°C/W
RθJC(top)Junction-to-case (top) thermal resistance70.249145.682.478.246.9°C/W
RθJBJunction-to-board thermal resistance64.14344.195.2112.659.7°C/W
ψJTJunction-to-top characterization parameter2516.934.11.815.25.1°C/W
ψJBJunction-to-board characterization parameter63.642.743.493.2111.259.1°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.