SNVSAU6A November 2017 – June 2021 LP87332D
When the input voltage falls below the VANAUVLO at the VANA pin, the buck and LDO regulators are disabled immediately (without switching ramp and shutdown delays), the output capacitor is discharged using the pulldown resistor, and the LP87332D device enters SHUTDOWN. When the V(VANA) voltage is above the VANAUVLO threshold level, the device powers up to STANDBY state.
If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register), then the RESET_REG_INT interrupt bit in the INT_TOP_2 register indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the RESET_REG_INT interrupt bit after detecting an nINT low signal, then it detects that the input supply voltage has been below the VANAUVLO level (or the host has requested reset with the SW_RESET bit in the RESET register), and the registers are reset to default values.