SNVSAU6A November 2017 – June 2021 LP87332D
The LP87332D device monitors the input voltage from the VANA pin in standby and active operation modes. If the input voltage rises above the VANAOVP voltage level, the following occurs:
The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above the overvoltage detection level, then the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit in the TOP_STAT register. The regulators cannot be enabled as long as the input voltage is above the overvoltage detection level or while the overvoltage interrupt is pending.