SNVSAU6A November 2017 – June 2021 LP87332D
PLL_CTRL is shown in Table 7-49, Address: 0x14
|Reserved - do not use||EN_PLL||Reserved - do not use||EXT_CLK_FREQ[4:0]|
|7||Reserved - do not use||R/W||0|
|6||EN_PLL||R/W||0||Selection of the external clock and PLL operation:|
0 - Forced to the internal RC oscillator. The PLL is disabled.
1 - PLL is enabled in the STANDBY and ACTIVE modes. Automatic external clock use when available, and interrupt is generated if the external clock appears or disappears.
|5||Reserved - do not use||R/W||0||This bit must be set to '''0.''|
|4:0||EXT_CLK_FREQ[4:0]||R/W||0x1||Frequency of the external clock (CLKIN):|
0x00 - 1 MHz
0x01 - 2 MHz
0x02 - 3 MHz
0x16 - 23 MHz
0x17 - 24 MHz
0x18...0x1F - Reserved - do not use
See electrical specification for the input clock frequency tolerance.