SBOSA11E March   2020  – December 2023 OPA206 , OPA2206 , OPA4206

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: OPA206
    5. 5.5 Thermal Information: OPA2206
    6. 5.6 Thermal Information: OPA4206
    7. 5.7 Electrical Characteristics: VS = ±5 V
    8. 5.8 Electrical Characteristics: VS = ±15 V
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Typical Specifications and Distributions
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Overvoltage Protection
      2. 7.3.2 Input Offset Trimming
      3. 7.3.3 Lower Input Bias With Super-Beta Inputs
      4. 7.3.4 Overload Power Limiter
      5. 7.3.5 EMI Rejection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Voltage Attenuator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier
      3. 8.2.3 Input Buffer and Protection for ADC Driver
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-29EBC737-06A3-4007-A4A6-DE53793BD13F-low.gif Figure 4-1 OPA206: D Package, 8-Pin SOIC (Top View)
Table 4-1 Pin Functions: OPA206
PIN TYPE DESCRIPTION
NAME NO.
+IN 3 Input Noninverting input
–IN 2 Input Inverting input
NC 1, 5, 8 — No internal connection (can be left floating)
OUT 6 Output Output
V+ 7 Power Positive (highest) power supply
V– 4 Power Negative (lowest) power supply
GUID-F2FB334B-6BDF-4E4D-9443-AFABE5EDF844-low.gif Figure 4-2 OPA2206: D Package, 8-pin SOIC and DGK Package, 8-Pin VSSOP (Top View)
Table 4-2 Pin Functions: OPA2206
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
–IN A 2 Input Inverting input, channel A
+IN B 5 Input Noninverting input, channel B
–IN B 6 Input Inverting input, channel B
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
V+ 8 Power Positive (highest) power supply
V– 4 Power Negative (lowest) power supply
GUID-99EF73CE-10E8-4CAB-A209-3CF1F21C8C43-low.gif Figure 4-3 OPA4206: D Package, 14-Pin SOIC and PW Package, 14-Pin TSSOP (Top View)
Table 4-3 Pin Functions: OPA4206
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
+IN B 5 Input Noninverting input, channel B
+IN C 10 Input Noninverting input, channel C
+IN D 12 Input Noninverting input, channel D
–IN A 2 Input Inverting input, channel A
–IN B 6 Input Inverting input, channel B
–IN C 9 Input Inverting input,channel C
–IN D 13 Input Inverting input, channel D
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
OUT C 8 Output Output, channel C
OUT D 14 Output Output, channel D
V+ 4 Power Positive (highest) power supply
V– 11 Power Negative (lowest) power supply