SBOSA11A March   2020  – March 2021 OPA2206

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA2206
    5. 6.5 Electrical Characteristics: VS = ±5 V
    6. 6.6 Electrical Characteristics: VS = ±15 V
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Typical Specifications and Distributions
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Overvoltage Protection
      2. 8.3.2 Input Offset Trimming
      3. 8.3.3 Lower Input Bias With Super-Beta Inputs
      4. 8.3.4 Overload Power Limiter
      5. 8.3.5 EMI Rejection
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Voltage Attenuator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier
      3. 9.2.3 Input Buffer and Protection for ADC Driver
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)

Table 6-1 Table of Graphs
DESCRIPTION FIGURE
Offset Voltage Production Distribution at 25°C Figure 6-1
Offset Voltage Distribution at 125°C Figure 6-2
Offset Voltage Distribution at -40°C Figure 6-3
Offset Voltage vs Temperature Figure 6-4
Offset Voltage Drift Production Distribution Figure 6-5
Offset Voltage vs Output Voltage Figure 6-6
Offset Voltage vs Power Supply Voltage Figure 6-7
Power-Supply Rejection Ratio vs Temperature Figure 6-8
Power-Supply and Common-Mode Rejection Ratio vs Frequency Figure 6-9
Common-Mode Rejection Ratio vs Temperature Figure 6-10
Offset Voltage vs Common-Mode Voltage Figure 6-11
Offset Voltage vs Vcm at Low Supply Figure 6-12
Offset Voltage vs Vcm at High Supply Figure 6-13
Open-Loop Gain and Phase vs Frequency Figure 6-14
Open-Loop Gain vs Distance from Supply Figure 6-15
Open-Loop Gain vs Temperature Figure 6-16
Closed-Loop Gain vs Frequency Figure 6-17
Input Bias Production Distribution Figure 6-18
Input Bias vs Common-Mode Voltage Figure 6-19
Input Bias and Input Offset Current vs Temperature Figure 6-20
Input Bias vs. Overvoltage Protected Common Mode Range Figure 6-21
Input Offset Current Production Distribution Figure 6-22
Voltage Noise Density vs Frequency Figure 6-23
0.1-Hz To 10-Hz Noise Figure 6-24
Total Harmonic Distortion + Noise Ratio vs Frequency Figure 6-25
Total Harmonic Distortion + Noise Ratio vs Output Amplitude Figure 6-26
Current Noise vs Frequency Figure 6-27
Maximum Output Voltage vs Frequency Figure 6-28
Output Voltage Swing vs Output Sourcing Current Figure 6-29
Output Voltage Swing vs Output Sinking Current Figure 6-30
Open-Loop Output Impedance vs Frequency Figure 6-31
No Phase Reversal Figure 6-32
Small-Signal Overshoot vs Capacitive Load, Gain = +1 Figure 6-34
Small-Signal Overshoot vs Capacitive Load, Gain = -1 Figure 6-34
Phase Margin vs Capacitive Load Figure 6-35
Positive Overload Recovery, Gain = -1 Figure 6-36
Negative Overload Recovery, Gain = -1 Figure 6-37
Settling Time Figure 6-38
Small-Signal Step Response, Gain = +1 Figure 6-39
Small-Signal Step Response, Gain = -1 Figure 6-40
Large-Signal Step Response, Gain = +1 Figure 6-41
Large-Signal Step Response, Gain = -1 Figure 6-42
Short-Circuit Current vs Temperature Figure 6-43
Electromagnetic Interference Rejection (EMIRR) Figure 6-44
Quiescent Current vs Supply Voltage Figure 6-45
Quiescent Current vs Temperature Figure 6-46
GUID-20210322-CA0I-KRTJ-VGFD-14ZRKNFNLTTX-low.svg
 
Figure 6-1 Offset Voltage Production Distribution at 25°C
GUID-20210322-CA0I-Q7CK-640F-66CFDGSZKRVM-low.svg
 
Figure 6-3 Offset Voltage Distribution at -40°C
GUID-20210322-CA0I-MQNP-KXC8-4ZRDPRNVSP9J-low.png
 
Figure 6-5 Offset Voltage Drift Production Distribution
GUID-20210322-CA0I-S308-LTMD-XJPBSDDC3FMZ-low.png
 
Figure 6-7 Offset Voltage vs Power Supply Voltage
GUID-20210322-CA0I-CZLM-LZ3D-KP4GKRQR9LLP-low.png
 
Figure 6-9 Power-Supply and Common-Mode Rejection Ratio vs Frequency
GUID-20210322-CA0I-5XN2-BWNN-Q9WGNHTBZ4T0-low.png
 
Figure 6-11 Offset Voltage vs Common-Mode Voltage
GUID-20210322-CA0I-HXLH-VFZK-PW2TDQK8JNCZ-low.png
 
Figure 6-13 Offset Voltage vs Vcm at High Supply
GUID-20210322-CA0I-PMWR-VG7W-ZNQW6WCRN0M2-low.png
 
Figure 6-15 Open-Loop Gain vs Distance from Supply
GUID-20210322-CA0I-RDJN-DHVG-ZZBLPJBPCFRD-low.svg
 
Figure 6-17 Closed-Loop Gain vs Frequency
GUID-20210322-CA0I-5KB1-TMH2-GSPLHGNXRXKT-low.png
 
Figure 6-19 Input Bias vs Common-Mode Voltage
GUID-20210322-CA0I-C8GX-NJWV-WC2NLQHMN21L-low.png
 
Figure 6-21 Input Bias vs. Overvoltage Protected Common Mode Range
GUID-20210322-CA0I-GZFC-ZJNQ-NQHF0DWX6RT9-low.png
 
Figure 6-23 Voltage Noise Density vs Frequency
GUID-20210322-CA0I-GR4W-WZCF-3BP0RWBSJFCX-low.png
 
Figure 6-25 Total Harmonic Distortion + Noise Ratio vs Frequency
GUID-20210322-CA0I-KVW6-L6NJ-ZC6ZSSNW6KL5-low.png
 
Figure 6-27 Current Noise vs Frequency
GUID-20210322-CA0I-2CJW-MVXP-K1QGDZDFSQ4V-low.png
 
Figure 6-29 Output Voltage Swing vs Output Sourcing Current
GUID-20210322-CA0I-WNPD-H1BX-MKMR9SHTP5LX-low.png
 
Figure 6-31 Open-Loop Output Impedance vs Frequency
GUID-20210322-CA0I-XTFJ-0BH4-BZFMBPXPR6FR-low.svg
  Gain = 1
Figure 6-33 Small-Signal Overshoot vs Capacitive Load
GUID-20210322-CA0I-SPQB-5NQD-PVTZGF1B6NNN-low.png
 
Figure 6-35 Phase Margin vs Capacitive Load
GUID-20210322-CA0I-FZXK-ZQKL-9V9PSGLJJHB2-low.svg
  Gain = –1
Figure 6-37 Negative Overload Recovery
GUID-20210322-CA0I-RKLG-WQD1-RLQ7MK5GWMTH-low.png
  Gain = 1
Figure 6-39 Small-Signal Step Response
GUID-20210322-CA0I-XRHC-BXCX-96HC8QS642KF-low.svg
  Gain = 1
Figure 6-41 Large-Signal Step Response
GUID-20210322-CA0I-ZCSB-DK5L-S09DHCMCWNTX-low.png
 
Figure 6-43 Short-Circuit Current vs Temperature
GUID-20210322-CA0I-ZQZX-ZZ6K-HGF7QT18KQS1-low.png
 
Figure 6-45 Quiescent Current vs Supply Voltage
GUID-20210322-CA0I-CPF5-PRTB-XWGS6DQZJXZR-low.svg
 
Figure 6-2 Offset Voltage Distribution at 125°C
GUID-20210322-CA0I-SPH2-PZPZ-PV4BN4VDFVLZ-low.png
 
Figure 6-4 Offset Voltage vs Temperature
GUID-20210322-CA0I-BBW3-KPMC-Z63LF87X7XL6-low.png
 
Figure 6-6 Offset Voltage vs Output Voltage
GUID-20210322-CA0I-FPVP-7WLX-K0LRQV83GRKN-low.png
 
Figure 6-8 Power-Supply Rejection Ratio vs Temperature
GUID-20210322-CA0I-FW9L-K2VV-XJVBWGBPKD2J-low.png
 
Figure 6-10 Common-Mode Rejection Ratio vs Temperature
GUID-20210322-CA0I-LMTJ-HXF6-N8V8QQDVJ6RS-low.png
 
Figure 6-12 Offset Voltage vs Vcm at Low Supply
GUID-20210322-CA0I-ZPWN-QMSJ-9WNMBKGTVZF7-low.png
 
Figure 6-14 Open-Loop Gain and Phase vs Frequency
GUID-20210322-CA0I-JXVB-DWFB-CBF0ZCMT1W5L-low.png
 
Figure 6-16 Open-Loop Gain vs Temperature
GUID-20210322-CA0I-NHXT-1XF4-WW6FGTCD563J-low.svg
 
Figure 6-18 Input Bias Production Distribution
GUID-20210322-CA0I-84ZK-FMMJ-QKQVSNWV9KR1-low.svg
 
Figure 6-20 Input Bias and Input Offset Current vs Temperature
GUID-20210322-CA0I-PWFL-QXTP-CNMKTCMJGH2L-low.svg
 
Figure 6-22 Input Offset Current Production Distribution
GUID-20210322-CA0I-0GFZ-VBC4-XVDBFSGTVHRM-low.png
 
Figure 6-24 0.1-Hz To 10-Hz Noise
GUID-20210322-CA0I-MNPH-GKFV-MBQLJBX9BQGK-low.png
 
Figure 6-26 Total Harmonic Distortion + Noise Ratio vs Output Amplitude
GUID-20210322-CA0I-GNC4-C2QJ-PHT0KDL2RPX1-low.png
 
Figure 6-28 Maximum Output Voltage vs Frequency
GUID-20210322-CA0I-3LJK-FHW2-CJXRQ9HVDRRV-low.png
 
Figure 6-30 Output Voltage Swing vs Output Sinking Current
GUID-20210322-CA0I-XKZR-WKGG-QKGBHB6D4JSJ-low.png
 
Figure 6-32 No Phase Reversal
GUID-20210322-CA0I-FH88-C32H-LTQFJPDPKPS8-low.svg
  Gain = -1
Figure 6-34 Small-Signal Overshoot vs Capacitive Load
GUID-20210322-CA0I-FWHV-NSXW-JTVGJBJ7WWKT-low.svg
  Gain = –1
Figure 6-36 Positive Overload Recovery
GUID-20210322-CA0I-SJNP-WLHL-DNDGBXHFG4DV-low.png
 
Figure 6-38 Settling Time
GUID-20210322-CA0I-TLFF-ZT41-WW3W1SQSTV8B-low.svg
  Gain = –1
Figure 6-40 Small-Signal Step Response
GUID-20210322-CA0I-Q62S-V91S-7MNHWKB04TKC-low.svg
  Gain = –1
Figure 6-42 Large-Signal Step Response
GUID-20210322-CA0I-DVJ8-L77S-FZF10S2ZGJJ8-low.svg
 
Figure 6-44 Electromagnetic Interference Rejection (EMIRR)
GUID-20210322-CA0I-ZJSQ-KMPK-ZZBQRZHLW0KV-low.png
 
Figure 6-46 Quiescent Current vs Temperature