SBOSAC8 December   2024 OPT4041

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 I2C Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Spectral Response
        1. 6.3.1.1 Channel 0: Human Eye Matching
        2. 6.3.1.2 Channel 1: Wide Band
      2. 6.3.2 Automatic Full-Scale Range Setting
      3. 6.3.3 Output Register CRC and Counter
        1. 6.3.3.1 Output Sample Counter
        2. 6.3.3.2 Output CRC
      4. 6.3.4 Threshold Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
      2. 6.4.2 Interrupt Modes of Operation
      3. 6.4.3 Light Range Selection
      4. 6.4.4 Selecting Conversion Time
      5. 6.4.5 Light Measurement in Lux
      6. 6.4.6 Threshold Detection Calculations
      7. 6.4.7 Light Resolution
    5. 6.5 Programming
      1. 6.5.1 I2C Bus Overview
        1. 6.5.1.1 Serial Bus Address
        2. 6.5.1.2 Serial Interface
      2. 6.5.2 Writing and Reading
        1. 6.5.2.1 High-Speed I2C Mode
        2. 6.5.2.2 Burst Read Mode
        3. 6.5.2.3 General-Call Reset Command
  8. 7 Register Maps
    1. 7.1 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Electrical Interface
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Optical Interface
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Optomechanical Design
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
        1. 8.5.2.1 Soldering and Handling Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.2.1 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors or active pullup devices. The controller generates a start condition followed by a valid serial byte containing the high-speed (HS) controller code 0000 1XXXb. This transmission is made in either standard mode or fast mode (up to 400kHz). The device does not acknowledge the HS controller code but does recognize the code and switches the internal filters to support a 2.6MHz operation.

The controller then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 2.6MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the bus in HS mode. A stop condition ends the HS mode and switches all internal filters of the device to support the F/S mode.