SBASA12 December 2020 PCM6020-Q1
PRODUCTION DATA
GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_TABLE_1 lists the memory-mapped registers for the Page 0 registers. All register offset addresses not listed in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
PAGE_CFG is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_PAGE_CFG_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_PAGE_CFG_TABLE.
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The device memory map is divided into pages. This register sets the page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PAGE[7:0] | |||||||
| R/W-00000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | PAGE[7:0] | R/W | 00000000b | These bits set the device page.
0d = Page 0 1d = Page 1 … 255d = Page 255 |
SW_RESET is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_SW_RESET_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_SW_RESET_TABLE.
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This register is the software reset register. Asserting a software reset places all register values in their default power-on-reset (POR) state.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SW_RESET | ||||||
| R-0000000b | R/W-0b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R | 0000000b | Reserved bits; Write only reset value |
| 0 | SW_RESET | R/W | 0b | Software reset. This bit is self-clearing.
0d = Do not reset 1d = Reset |
SLEEP_CFG is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_SLEEP_CFG_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_SLEEP_CFG_TABLE.
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This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | VREF_QCHG[1:0] | I2C_BRDCAST_EN | RESERVED | SLEEP_ENZ | ||
| R/W-0b | R/W-00b | R/W-00b | R/W-0b | R-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 6-5 | RESERVED | R/W | 00b | Reserved bits; Write only reset values |
| 4-3 | VREF_QCHG[1:0] | R/W | 00b | The duration of the quick-charge for the VREF external capacitor is set using an internal series impedance of 200 Ω.
0d = VREF quick-charge duration of 3.5 ms (typical) 1d = VREF quick-charge duration of 10 ms (typical) 2d = VREF quick-charge duration of 50 ms (typical) 3d = VREF quick-charge duration of 100 ms (typical) |
| 2 | I2C_BRDCAST_EN | R/W | 0b | I2C broadcast addressing setting.
0d = I2C broadcast mode disabled; the I2C slave address is determined based on the ADDR pins 1d = I2C broadcast mode enabled; the I2C slave address is fixed at 1001 100 |
| 1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 0 | SLEEP_ENZ | R/W | 0b | Sleep mode setting.
0d = Device is in sleep mode 1d = Device is not in sleep mode |
SHDN_CFG is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_SHDN_CFG_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_SHDN_CFG_TABLE.
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This register configures the device shutdown
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SHDNZ_CFG[1:0] | DREG_KA_TIME[1:0] | |||||
| R-0000b | R/W-01b | R/W-01b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
| 3-2 | SHDNZ_CFG[1:0] | R/W | 01b | Shutdown configuration.
0d = DREG is powered down immediately after SHDNZ asserts 1d = DREG remains active to enable a clean shut down until a time-out is reached; after the time-out period, DREG is forced to power off 2d = DREG remains active until the device cleanly shuts down 3d = Reserved |
| 1-0 | DREG_KA_TIME[1:0] | R/W | 01b | These bits set how long DREG remains active after SHDNZ asserts.
0d = DREG remains active for 30 ms (typical) 1d = DREG remains active for 25 ms (typical) 2d = DREG remains active for 10 ms (typical) 3d = DREG remains active for 5 ms (typical) |
ASI_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CFG0_TABLE.
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This register is the ASI configuration register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ASI_FORMAT[1:0] | ASI_WLEN[1:0] | FSYNC_POL | BCLK_POL | TX_EDGE | TX_FILL | ||
| R/W-00b | R/W-11b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | ASI_FORMAT[1:0] | R/W | 00b | ASI protocol format.
0d = TDM mode 1d = I2S mode 2d = LJ (left-justified) mode 3d = Reserved |
| 5-4 | ASI_WLEN[1:0] | R/W | 11b | ASI word or slot length.
0d = 16 bits 1d = 20 bits 2d = 24 bits 3d = 32 bits |
| 3 | FSYNC_POL | R/W | 0b | ASI FSYNC polarity.
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
| 2 | BCLK_POL | R/W | 0b | ASI BCLK polarity.
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
| 1 | TX_EDGE | R/W | 0b | ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in bit 2 (BCLK_POL) 1d = Inverted following edge (half cycle delay) with respect to the default edge setting |
| 0 | TX_FILL | R/W | 0b | ASI data output (on the primary and secondary data pin) for any unused cycles
0d = Always transmit 0 for unused cycles 1d = Always use Hi-Z for unused cycles |
ASI_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CFG1_TABLE.
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This register is the ASI configuration register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TX_LSB | TX_KEEPER[1:0] | TX_OFFSET[4:0] | |||||
| R/W-0b | R/W-00b | R/W-00000b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | TX_LSB | R/W | 0b | ASI data output (on the primary and secondary data pin) for LSB transmissions.
0d = Transmit the LSB for a full cycle 1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle |
| 6-5 | TX_KEEPER[1:0] | R/W | 00b | ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled 1d = Bus keeper is always enabled 2d = Bus keeper is enabled during LSB transmissions only for one cycle 3d = Bus keeper is enabled during LSB transmissions only for one and half cycles |
| 4-0 | TX_OFFSET[4:0] | R/W | 00000b | ASI data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol |
ASI_CFG2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CFG2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CFG2_TABLE.
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This register is the ASI configuration register 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ASI_DAISY | RESERVED | ASI_ERR | ASI_ERR_RCOV | RESERVED | |||
| R/W-0b | R-0b | R/W-0b | R/W-0b | R-0000b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ASI_DAISY | R/W | 0b | ASI daisy chain connection.
0d = All devices are connected in the common ASI bus 1d = All devices are daisy-chained for the ASI bus |
| 6 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 5 | ASI_ERR | R/W | 0b | ASI bus error detection.
0d = Enable bus error detection 1d = Disable bus error detection |
| 4 | ASI_ERR_RCOV | R/W | 0b | ASI bus error auto resume.
0d = Enable auto resume after bus error recovery 1d = Disable auto resume after bus error recovery and remain powered down until the host configures the device |
| 3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
ASI_CH1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CH1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CH1_TABLE.
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This register is the ASI slot configuration register for channel 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH1_OUTPUT | CH1_SLOT[5:0] | |||||
| R-0b | R/W-0b | R/W-000000b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 6 | CH1_OUTPUT | R/W | 0b | Channel 1 output line.
0d = Channel 1 output is on the ASI primary output pin (SDOUT) 1d = Channel 1 output is on the ASI secondary output pin (GPIO1 or GPOx) |
| 5-0 | CH1_SLOT[5:0] | R/W | 000000b | Channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is left slot 31 32d = TDM is slot 32 or I2S, LJ is right slot 0 33d = TDM is slot 33 or I2S, LJ is right slot 1 34d to 62d = Slot assigned as per configuration 63d = TDM is slot 63 or I2S, LJ is right slot 31 |
ASI_CH2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CH2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_CH2_TABLE.
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This register is the ASI slot configuration register for channel 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH2_OUTPUT | CH2_SLOT[5:0] | |||||
| R-0b | R/W-0b | R/W-000001b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 6 | CH2_OUTPUT | R/W | 0b | Channel 2 output line.
0d = Channel 2 output is on the ASI primary output pin (SDOUT) 1d = Channel 2 output is on the ASI secondary output pin (GPIO1 or GPOx) |
| 5-0 | CH2_SLOT[5:0] | R/W | 000001b | Channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is left slot 31 32d = TDM is slot 32 or I2S, LJ is right slot 0 33d = TDM is slot 33 or I2S, LJ is right slot 1 34d to 62d = Slot assigned as per configuration 63d = TDM is slot 63 or I2S, LJ is right slot 31 |
MST_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MST_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MST_CFG0_TABLE.
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This register is the ASI master mode configuration register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MST_SLV_CFG | AUTO_CLK_CFG | AUTO_MODE_PLL_DIS | BCLK_FSYNC_GATE | FS_MODE | MCLK_FREQ_SEL[2:0] | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-010b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | MST_SLV_CFG | R/W | 0b | ASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to the device) 1d = Device is in master mode (both BCLK and FSYNC are generated from the device) |
| 6 | AUTO_CLK_CFG | R/W | 0b | Automatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and PLL configurations are auto derived) 1d = Auto clock configuration is disabled (custom mode and device GUI must be used for the device configuration settings) |
| 5 | AUTO_MODE_PLL_DIS | R/W | 0b | Automatic mode PLL setting.
0d = PLL is enabled in auto clock configuration 1d = PLL is disabled in auto clock configuration |
| 4 | BCLK_FSYNC_GATE | R/W | 0b | BCLK and FSYNC clock gate (valid when the device is in master mode).
0d = Do not gate BCLK and FSYNC 1d = Force gate BCLK and FSYNC when being transmitted from the device in master mode |
| 3 | FS_MODE | R/W | 0b | Sample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz 1d = fS is a multiple (or submultiple) of 44.1 kHz |
| 2-0 | MCLK_FREQ_SEL[2:0] | R/W | 010b | These bits select the MCLK (GPIO or GPIx) frequency for the PLL source clock input (valid when the device is in master mode and MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz 1d = 12.288 MHz 2d = 13 MHz 3d = 16 MHz 4d = 19.2 MHz 5d = 19.68 MHz 6d = 24 MHz 7d = 24.576 MHz |
MST_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MST_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MST_CFG1_TABLE.
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This register is the ASI master mode configuration register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FS_RATE[3:0] | FS_BCLK_RATIO[3:0] | ||||||
| R/W-0100b | R/W-1000b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | FS_RATE[3:0] | R/W | 0100b | Programmed sample rate of the ASI bus (not used when the device is configured in slave mode auto clock configuration).
0d = 7.35 kHz or 8 kHz 1d = 14.7 kHz or 16 kHz 2d = 22.05 kHz or 24 kHz 3d = 29.4 kHz or 32 kHz 4d = 44.1 kHz or 48 kHz 5d = 88.2 kHz or 96 kHz 6d = 176.4 kHz or 192 kHz 7d = 352.8 kHz or 384 kHz 8d = 705.6 kHz or 768 kHz 9d to 15d = Reserved |
| 3-0 | FS_BCLK_RATIO[3:0] | R/W | 1000b | Programmed BCLK to FSYNC frequency ratio of the ASI bus (not used when the device is configured in slave mode auto clock configuration).
0d = Ratio of 16 1d = Ratio of 24 2d = Ratio of 32 3d = Ratio of 48 4d = Ratio of 64 5d = Ratio of 96 6d = Ratio of 128 7d = Ratio of 192 8d = Ratio of 256 9d = Ratio of 384 10d = Ratio of 512 11d = Ratio of 1024 12d = Ratio of 2048 13d = Reserved 14d = Reserved 15d = Reserved |
ASI_STS is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_STS_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_STS_TABLE.
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This register s the ASI bus clock monitor status register
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FS_RATE_STS[3:0] | FS_RATIO_STS[3:0] | ||||||
| R-1111b | R-1111b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | FS_RATE_STS[3:0] | R | 1111b | Detected sample rate of the ASI bus.
0d = 7.35 kHz or 8 kHz 1d = 14.7 kHz or 16 kHz 2d = 22.05 kHz or 24 kHz 3d = 29.4 kHz or 32 kHz 4d = 44.1 kHz or 48 kHz 5d = 88.2 kHz or 96 kHz 6d = 176.4 kHz or 192 kHz 7d = 352.8 kHz or 384 kHz 8d = 705.6 kHz or 768 kHz 9d to 14d = Reserved 15d = Invalid sample rate |
| 3-0 | FS_RATIO_STS[3:0] | R | 1111b | Detected BCLK to FSYNC frequency ratio of the ASI bus.
0d = Ratio of 16 1d = Ratio of 24 2d = Ratio of 32 3d = Ratio of 48 4d = Ratio of 64 5d = Ratio of 96 6d = Ratio of 128 7d = Ratio of 192 8d = Ratio of 256 9d = Ratio of 384 10d = Ratio of 512 11d = Ratio of 1024 12d = Ratio of 2048 13d = Reserved 14d = Reserved 15d = Invalid ratio |
CLK_SRC is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CLK_SRC_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CLK_SRC_TABLE.
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This register is the clock source configuration register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DIS_PLL_SLV_CLK_SRC | MCLK_FREQ_SEL_MODE | MCLK_RATIO_SEL[2:0] | RESERVED | ||||
| R/W-0b | R/W-0b | R/W-010b | R-000b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DIS_PLL_SLV_CLK_SRC | R/W | 0b | Audio root clock source setting when the device is configured with the PLL disabled in the auto clock configuration for slave mode (AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source 1d = MCLK (GPIOx or GPIx) is used as the audio root clock source (the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting) |
| 6 | MCLK_FREQ_SEL_MODE | R/W | 0b | Master mode MCLK (GPIOx or GPIx) frequency selection mode (valid when the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19) configuration 1d = MCLK frequency is specified as a multiple of FSYNC in the MCLK_RATIO_SEL (P0_R22) configuration |
| 5-3 | MCLK_RATIO_SEL[2:0] | R/W | 010b | These bits select the MCLK (GPIOx or GPIx) to FSYNC ratio for master mode or when MCLK is used as the audio root clock source in slave mode.
0d = Ratio of 64 1d = Ratio of 256 2d = Ratio of 384 3d = Ratio of 512 4d = Ratio of 768 5d = Ratio of 1024 6d = Ratio of 1536 7d = Ratio of 2304 |
| 2-0 | RESERVED | R | 000b | Reserved bits; Write only reset values |
GPIO_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_CFG0_TABLE.
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This register is the GPIO configuration register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO1_CFG[3:0] | RESERVED | GPIO1_DRV[2:0] | |||||
| R/W-0010b | R-0b | R/W-010b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | GPIO1_CFG[3:0] | R/W | 0010b | GPIO1 configuration.
0d = GPIO1 is disabled 1d = GPIO1 is configured as a general-purpose output (GPO) 2d = GPIO1 is configured as a device interrupt output (IRQ) 3d = GPIO1 is configured as a secondary ASI output (SDOUT2) Dont use 5d = Reserved 6d = Reserved 7d = GPIO1 is configured as an input to power down all ADC channels 8d = GPIO1 is configured as an input to control when MICBIAS turns on or off (MICBIAS_EN) 9d = GPIO1 is configured as a general-purpose input (GPI) 10d = GPIO1 is configured as a master clock input (MCLK) 11d = GPIO1 is configured as an ASI input for daisy-chain (SDIN) 12d = Reserved 13d = Reserved Dont use Dont use |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2-0 | GPIO1_DRV[2:0] | R/W | 010b | GPIO1 output drive configuration (not used when GPIO1 is configured as SDOUT2).
0d = Hi-Z output 1d = Drive active low and active high 2d = Drive active low and weak high 3d = Drive active low and Hi-Z 4d = Drive weak low and active high 5d = Drive Hi-Z and active high 6d to 7d = Reserved |
GPIO_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_CFG1_TABLE.
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This register is the GPIO configuration register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO2_CFG[3:0] | RESERVED | GPIO2_DRV[2:0] | |||||
| R/W-0000b | R-0b | R/W-000b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | GPIO2_CFG[3:0] | R/W | 0000b | GPIO2 configuration.
0d = GPIO2 is disabled 1d = GPIO2 is configured as a general-purpose output (GPO) 2d = GPIO2 is configured as a device interrupt output (IRQ) 3d = GPIO2 is configured as a secondary ASI output (SDOUT2) Dont use 5d = Reserved 6d = Reserved 7d = GPIO2 is configured as an input to power down all ADC channels 8d = GPIO2 is configured as an input to control when MICBIAS turns on or off (MICBIAS_EN) 9d = GPIO2 is configured as a general-purpose input (GPI) 10d = GPIO2 is configured as a master clock input (MCLK) 11d = GPIO2 is configured as an ASI input for daisy-chain (SDIN) 12d = Reserved 13d = Reserved Dont use Dont use |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2-0 | GPIO2_DRV[2:0] | R/W | 000b | GPIO2 output drive configuration (not used when GPIO2 is configured as SDOUT2).
0d = Hi-Z output 1d = Drive active low and active high 2d = Drive active low and weak high 3d = Drive active low and Hi-Z 4d = Drive weak low and active high 5d = Drive Hi-Z and active high 6d to 7d = Reserved |
GPIO_CFG2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_CFG2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_CFG2_TABLE.
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This register is the GPIO configuration register 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO3_CFG[3:0] | RESERVED | GPIO3_DRV[2:0] | |||||
| R/W-0000b | R-0b | R/W-000b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | GPIO3_CFG[3:0] | R/W | 0000b | GPIO3 configuration.
0d = GPIO3 is disabled 1d = GPIO3 is configured as a general-purpose output (GPO) 2d = GPIO3 is configured as a device interrupt output (IRQ) 3d = GPIO3 is configured as a secondary ASI output (SDOUT2) Dont use 5d = Reserved 6d = Reserved 7d = GPIO3 is configured as an input to power down all ADC channels 8d = GPIO3 is configured as an input to control when MICBIAS turns on or off (MICBIAS_EN) 9d = GPIO3 is configured as a general-purpose input (GPI) 10d = GPIO3 is configured as a master clock input (MCLK) 11d = GPIO3 is configured as an ASI input for daisy-chain (SDIN) 12d = Reserved 13d = Reserved Dont use Dont use |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2-0 | GPIO3_DRV[2:0] | R/W | 000b | GPIO3 output drive configuration (not used when GPIO3 is configured as SDOUT2).
0d = Hi-Z output 1d = Drive active low and active high 2d = Drive active low and weak high 3d = Drive active low and Hi-Z 4d = Drive weak low and active high 5d = Drive Hi-Z and active high 6d to 7d = Reserved |
GPI_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPI_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPI_CFG0_TABLE.
Return to the Summary Table.
This register is the GPI configuration register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPI1_CFG[3:0] | RESERVED | ||||||
| R/W-0000b | R-0000b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | GPI1_CFG[3:0] | R/W | 0000b | GPI1 configuration.
0d = GPI1 is disabled 1d to 6d = Reserved 7d = GPI1 is configured as an input to power down all ADC channels 8d = GPI1 is configured as an input to control when MICBIAS turns on or off (MICBIAS_EN) 9d = GPI1 is configured as a general-purpose input (GPI) 10d = GPI1 is configured as a master clock input (MCLK) 11d = GPI1 is configured as an ASI input for daisy-chain (SDIN) 12d = Reserved 13d = Reserved Dont use Dont use |
| 3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
GPI_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPI_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPI_CFG1_TABLE.
Return to the Summary Table.
This register is the GPI configuration register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPI2_CFG[3:0] | RESERVED | ||||||
| R/W-0000b | R-0000b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | GPI2_CFG[3:0] | R/W | 0000b | GPI2 configuration.
0d = GPI2 is disabled 1d to 6d = Reserved 7d = GPI2 is configured as an input to power down all ADC channels 8d = GPI2 is configured as an input to control when MICBIAS turns on or off (MICBIAS_EN) 9d = GPI2 is configured as a general-purpose input (GPI) 10d = GPI2 is configured as a master clock input (MCLK) 11d = GPI2 is configured as an ASI input for daisy-chain (SDIN) 12d = Reserved 13d = Reserved Dont use Dont use |
| 3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
GPIO_VAL is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_VAL_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_VAL_TABLE.
Return to the Summary Table.
This register is the GPIO output value register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO1_VAL | GPIO2_VAL | GPIO3_VAL | RESERVED | ||||
| R/W-0b | R/W-0b | R/W-0b | R-00000b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO1_VAL | R/W | 0b | GPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0 1d = Drive the output with a value of 1 |
| 6 | GPIO2_VAL | R/W | 0b | GPIO2 output value when configured as a GPO.
0d = Drive the output with a value of 0 1d = Drive the output with a value of 1 |
| 5 | GPIO3_VAL | R/W | 0b | GPIO3 output value when configured as a GPO.
0d = Drive the output with a value of 0 1d = Drive the output with a value of 1 |
| 4-0 | RESERVED | R | 00000b | Reserved bits; Write only reset value |
GPIO_MON is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_MON_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_GPIO_MON_TABLE.
Return to the Summary Table.
This register is the GPIO monitor value register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO1_MON | GPIO2_MON | GPIO3_MON | GPI1_MON | GPI2_MON | RESERVED | ||
| R-0b | R-0b | R-0b | R-0b | R-0b | R-000b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO1_MON | R | 0b | GPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
| 6 | GPIO2_MON | R | 0b | GPIO2 monitor value when configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
| 5 | GPIO3_MON | R | 0b | GPIO3 monitor value when configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
| 4 | GPI1_MON | R | 0b | GPI1 monitor value when configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
| 3 | GPI2_MON | R | 0b | GPI2 monitor value when configured as a GPI.
0d = Input monitor value 0 1d = Input monitor value 1 |
| 2-0 | RESERVED | R | 000b | Reserved bits; Write only reset value |
INT_CFG is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_CFG_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_CFG_TABLE.
Return to the Summary Table.
This regiser is the interrupt configuration register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_POL | INT_EVENT[1:0] | PD_ON_FLT_CFG[1:0] | LTCH_READ_CFG | PD_ON_FLT_RCV_CFG | LTCH_CLR_ON_READ | ||
| R/W-0b | R/W-00b | R/W-00b | R/W-0b | R/W-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_POL | R/W | 0b | Interrupt polarity.
0d = Active low (IRQZ) 1d = Active high (IRQ) |
| 6-5 | INT_EVENT[1:0] | R/W | 00b | Interrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event Dont use 2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event 3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event |
| 4-3 | PD_ON_FLT_CFG[1:0] | R/W | 00b | Powerdown configuration when fault detected for any channel or MICBIAS fault detected.
0d = Faults event are not used for ADC and MICBIAS power down. It is recommend to set these bits as 2d to shutdown the blocks for which fault occurred. 1d = Only unmasked faults are used for power down of respective ADC channel; In case of MICBIAS fault detected, MICBIAS and all ADC channels gets powered-down based on P0_R58 settings 2d = Both masked or unmasked faults are used for power down of respective ADC channel; In case of MICBIAS fault detected, MICBIAS and all ADC channels gets powered-down based on P0_R58 settings. 3d = Reserved |
| 2 | LTCH_READ_CFG | R/W | 0b | Interrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers 1d = Only unmasked interrupts can be read through the LTCH registers |
| 1 | PD_ON_FLT_RCV_CFG | R/W | 0b | Recovery configuration for ADC channels when fault goes away.
0d = Auto recovery, ADC channels are re-powered up when fault goes away 1d = Manual recovery, ADC channels are required to power-up manually using P0_R119 when fault goes away |
| 0 | LTCH_CLR_ON_READ | R/W | 0b | Configuration for clearing LTCH register bits.
0d = LTCH register bits are cleared on register read only if live status is zero 1d = LTCH register bits are cleared on register read irrespective of live status and set only if live status goes again low to high |
INT_MASK0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK0_TABLE.
Return to the Summary Table.
This register is the interrupt masks register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_MASK0 | INT_MASK0 | INT_MASK0 | INT_MASK0 | RESERVED | RESERVED | RESERVED | RESERVED |
| R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_MASK0 | R/W | 1b | ASI clock error mask.
0d = Unmask 1d = Mask |
| 6 | INT_MASK0 | R/W | 1b | PLL lock interrupt mask.
0d = Unmask 1d = Mask |
| 5 | INT_MASK0 | R/W | 1b | Boost or MICBIAS over temperature interrupt mask.
0d = Unmask 1d = Mask |
| 4 | INT_MASK0 | R/W | 1b | Boost or MICBIAS over current interrupt mask.
0d = Unmask 1d = Mask |
| 3 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 2 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 1 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 0 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
INT_MASK1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK1_TABLE.
Return to the Summary Table.
This register is the interrupt masks register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_MASK1 | INT_MASK1 | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-1b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_MASK1 | R/W | 0b | Channel 1 input DC faults diagnostic interrupt mask.
0d = Unmask 1d = Mask |
| 6 | INT_MASK1 | R/W | 0b | Channel 2 input DC faults diagnostic interrupt mask.
0d = Unmask 1d = Mask |
| 5 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 1 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 0 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
INT_MASK2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK2_TABLE.
Return to the Summary Table.
This register is the interrupt masks register 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_MASK2 | R/W | 0b | Input diagnostics; Open inputs fault interrupt mask.
0d = Unmask 1d = Mask |
| 6 | INT_MASK2 | R/W | 0b | Input diagnostics; Inputs shorted fault interrupt mask.
0d = Unmask 1d = Mask |
| 5 | INT_MASK2 | R/W | 0b | Input diagnostics; INxP shorted to ground fault interrupt mask.
0d = Unmask 1d = Mask |
| 4 | INT_MASK2 | R/W | 0b | Input diagnostics; INxM shorted to ground fault interrupt mask.
0d = Unmask 1d = Mask |
| 3 | INT_MASK2 | R/W | 0b | Input diagnostics; INxP shorted to MICBIAS fault interrupt mask.
0d = Unmask 1d = Mask |
| 2 | INT_MASK2 | R/W | 0b | Input diagnostics; INxM shorted to MICBIAS fault interrupt mask.
0d = Unmask 1d = Mask |
| 1 | INT_MASK2 | R/W | 0b | Input diagnostics; INxP shorted to VBAT_IN fault interrupt mask.
0d = Unmask 1d = Mask |
| 0 | INT_MASK2 | R/W | 0b | Input diagnostics; INxM shorted to VBAT_IN fault interrupt mask.
0d = Unmask 1d = Mask |
INT_LTCH0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH0_TABLE.
Return to the Summary Table.
This register is the latched Interrupt readback register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | RESERVED | RESERVED | RESERVED | RESERVED |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_LTCH0 | R | 0b | Fault status for an ASI bus clock error (self-clearing bit).
0d = No fault detected 1d = Fault detected |
| 6 | INT_LTCH0 | R | 0b | Status of PLL lock (self-clearing bit).
0d = No PLL lock detected 1d = PLL lock detected |
| 5 | INT_LTCH0 | R | 0b | Fault status for boost or MICBIAS over temperature (self-clearing bit).
0d = No fault detected 1d = Fault detected |
| 4 | INT_LTCH0 | R | 0b | Fault status for boost or MICBIAS over current (self-clearing bit).
0d = No fault detected 1d = Fault detected |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CHx_LTCH is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CHX_LTCH_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CHX_LTCH_TABLE.
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This register is the latched Interrupt status register for channel level diagnostic summary.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STS_CHx_LTCH | STS_CHx_LTCH | RESERVED | RESERVED | RESERVED | RESERVED | STS_CHx_LTCH | RESERVED |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | STS_CHx_LTCH | R | 0b | Status of CH1_LTCH (self-clearing bit).
0d = No faults occurred in channel 1 1d = Atleast a fault has occurred in channel 1 |
| 6 | STS_CHx_LTCH | R | 0b | Status of CH2_LTCH (self-clearing bit).
0d = No faults occurred in channel 2 1d = Atleast a fault has occurred in channel 2 |
| 5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 1 | STS_CHx_LTCH | R | 0b | Status of short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS (self-clearing bit).
0d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has not occurred in any channel 1d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in atleast one channel |
| 0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CH1_LTCH is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_LTCH_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_LTCH_TABLE.
Return to the Summary Table.
This register is the latched Interrupt status register for channel 1 fault diagnostic
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_LTCH | CH1_LTCH | CH1_LTCH | CH1_LTCH | CH1_LTCH | CH1_LTCH | CH1_LTCH | CH1_LTCH |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CH1_LTCH | R | 0b | Channel 1 open input fault status (self-clearing bit).
0d = No open input detected 1d = Open input detected |
| 6 | CH1_LTCH | R | 0b | Channel 1 input pair short fault status (self-clearing bit).
0d = No input pair short detected 1d = Input short to each other detected |
| 5 | CH1_LTCH | R | 0b | Channel 1 IN1P short to ground fault status (self-clearing bit).
0d = IN1P no short to ground detected 1d = IN1P short to ground detected |
| 4 | CH1_LTCH | R | 0b | Channel 1 IN1M short to ground fault status (self-clearing bit).
0d = IN1M no short to ground detected 1d = IN1M short to ground detected |
| 3 | CH1_LTCH | R | 0b | Channel 1 IN1P short to MICBIAS fault status (self-clearing bit).
0d = IN1P no short to MICBIAS detected 1d = IN1P short to MICBIAS detected |
| 2 | CH1_LTCH | R | 0b | Channel 1 IN1M short to MICBIAS fault status (self-clearing bit).
0d = IN1M no short to MICBIAS detected 1d = IN1M short to MICBIAS detected |
| 1 | CH1_LTCH | R | 0b | Channel 1 IN1P short to VBAT_IN fault status (self-clearing bit).
0d = IN1P no short to VBAT_IN detected 1d = IN1P short to VBAT_IN detected |
| 0 | CH1_LTCH | R | 0b | Channel 1 IN1M short to VBAT_IN fault status (self-clearing bit - This bit gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN1M no short to VBAT_IN detected 1d = IN1M short to VBAT_IN detected |
CH2_LTCH is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_LTCH_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_LTCH_TABLE.
Return to the Summary Table.
This register is the latched Interrupt status register for channel 2 fault diagnostic.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH2_LTCH | CH2_LTCH | CH2_LTCH | CH2_LTCH | CH2_LTCH | CH2_LTCH | CH2_LTCH | CH2_LTCH |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CH2_LTCH | R | 0b | Channel 2 open input fault status (self-clearing bit).
0d = No open input detected 1d = Open input detected |
| 6 | CH2_LTCH | R | 0b | Channel 2 input pair short fault status (self-clearing bit).
0d = No input pair short detected 1d = Input short to each other detected |
| 5 | CH2_LTCH | R | 0b | Channel 2 IN2P short to ground fault status (self-clearing bit).
0d = IN2P no short to ground detected 1d = IN2P short to ground detected |
| 4 | CH2_LTCH | R | 0b | Channel 2 IN2M short to ground fault status (self-clearing bit).
0d = IN2M no short to ground detected 1d = IN2M short to ground detected |
| 3 | CH2_LTCH | R | 0b | Channel 2 IN2P short to MICBIAS fault status (self-clearing bit).
0d = IN2P no short to MICBIAS detected 1d = IN2P short to MICBIAS detected |
| 2 | CH2_LTCH | R | 0b | Channel 2 IN2M short to MICBIAS fault status (self-clearing bit).
0d = IN2M no short to MICBIAS detected 1d = IN2M short to MICBIAS detected |
| 1 | CH2_LTCH | R | 0b | Channel 2 IN2P short to VBAT_IN fault status (self-clearing bit).
0d = IN2P no short to VBAT_IN detected 1d = IN2P short to VBAT_IN detected |
| 0 | CH2_LTCH | R | 0b | Channel 2 IN2M short to VBAT_IN fault status (self-clearing bit - This bit gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN2M no short to VBAT_IN detected 1d = IN2M short to VBAT_IN detected |
INT_MASK3 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK3_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_MASK3_TABLE.
Return to the Summary Table.
This register is the interrupt masks register 3.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_MASK3 | INT_MASK3 | INT_MASK3 | INT_MASK3 | INT_MASK3 | RESERVED | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-000b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_MASK3 | R/W | 0b | INxP over voltage fault mask.
0d = Unmask 1d = Mask |
| 6 | INT_MASK3 | R/W | 0b | INxM over voltage fault mask.
0d = Unmask 1d = Mask |
| 5 | INT_MASK3 | R/W | 0b | MICBIAS high current fault mask.
0d = Unmask 1d = Mask |
| 4 | INT_MASK3 | R/W | 0b | MICBIAS low current fault mask.
0d = Unmask 1d = Mask |
| 3 | INT_MASK3 | R/W | 0b | MICBIAS over voltage fault mask.
0d = Unmask 1d = Mask |
| 2-0 | RESERVED | R | 000b | Reserved bits; Write only reset value |
INT_LTCH1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH1_TABLE.
Return to the Summary Table.
This register is the latched Interrupt readback register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_LTCH1 | INT_LTCH1 | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-00b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_LTCH1 | R | 0b | Channel 1 IN1P over voltage fault status (self-clearing bit - This bit gets clear on reading Page-0, Register-46d, CH1_LTCH register).
0d = No IN1P over voltage fault detected 1d = IN1P over voltage fault has detected |
| 6 | INT_LTCH1 | R | 0b | Channel 2 IN2P over voltage fault status (self-clearing bit - This bit gets clear on reading Page-0, Register-47d, CH2_LTCH register).
0d = No IN2P over voltage fault detected 1d = IN2P over voltage fault has detected |
| 5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 1-0 | RESERVED | R | 00b | Reserved bits; Write only reset value |
INT_LTCH2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH2_TABLE.
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This register is the latched Interrupt readback register 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_LTCH2 | INT_LTCH2 | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-00b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_LTCH2 | R | 0b | Channel 1 IN1M over voltage fault status (self-clearing bit - This bit gets clear on reading Page-0, Register-46d, CH1_LTCH register).
0d = No IN1M over voltage fault detected 1d = IN1M over voltage fault has detected |
| 6 | INT_LTCH2 | R | 0b | Channel 2 IN2M over voltage fault status (self-clearing bit - This bit gets clear on reading Page-0, Register-47d, CH2_LTCH register).
0d = No IN2M over voltage fault detected 1d = IN2M over voltage fault has detected |
| 5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 1-0 | RESERVED | R | 00b | Reserved bits; Write only reset value |
INT_LTCH3 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH3_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_INT_LTCH3_TABLE.
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This register is the latched Interrupt readback register 3.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT_LTCH3 | INT_LTCH3 | INT_LTCH3 | RESERVED | ||||
| R-0b | R-0b | R-0b | R-00000b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_LTCH3 | R | 0b | Fault status for MICBIAS high current (self-clearing bit).
0d = No fault detected 1d = Fault detected |
| 6 | INT_LTCH3 | R | 0b | Fault status for MICBIAS low current (self-clearing bit)
0d = No fault detected 1d = Fault detected |
| 5 | INT_LTCH3 | R | 0b | Fault status for MICBIAS over voltage (self-clearing bit).
0d = No fault detected 1d = Fault detected |
| 4-0 | RESERVED | R | 00000b | Reserved bits; Write only reset value |
MBDIAG_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MBDIAG_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MBDIAG_CFG0_TABLE.
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This register is the MICBIAS diagnostic configuration register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MBIAS_HIGH_CURR_THRS[7:0] | |||||||
| R/W-10111010b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | MBIAS_HIGH_CURR_THRS[7:0] | R/W | 10111010b | Threshold for MICBIAS high load current fault diagnostic.
0d to 56d = Reserved 57d = High load current threshold is set as 0 mA (typ) 58d = High load current threshold is set as 0.54 mA (typ) 59d = High load current threshold is set as 1.08 mA (typ) 60d to 185d = High load current threshold is set as per configuration 186d = High load current threshold is set as 69.66 mA (typ) 187d to 241d = High load current threshold is set as per configuration 242d = High load current threshold is set as 99.90 mA (typ) 243d to 255d = Reserved |
MBDIAG_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MBDIAG_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MBDIAG_CFG1_TABLE.
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This register is the MICBIAS diagnostic configuration register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MBIAS_LOW_CURR_THRS[7:0] | |||||||
| R/W-01001011b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | MBIAS_LOW_CURR_THRS[7:0] | R/W | 01001011b | Threshold for MICBIAS low load current fault diagnostic.
0d to 56d = Reserved 57d = Low load current threshold is set as 0 mA (typ) 58d = Low load current threshold is set as 0.54 mA (typ) 59d = Low load current threshold is set as 1.08 mA (typ) 60d to 74d = Low load current threshold is set as per configuration 75d = Low load current threshold is set as 9.72 mA (typ) 76d to 241d = Low load current threshold is set as per configuration 242d = Low load current threshold is set as 99.90 mA (typ) 243d to 255d = Reserved |
MBDIAG_CFG2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MBDIAG_CFG2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_MBDIAG_CFG2_TABLE.
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This register is the MICBIAS diagnostic configuration register 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PD_MBIAS_FAULT1 | PD_MBIAS_FAULT2 | PD_MBIAS_FAULT3 | PD_MBIAS_FAULT4 | RESERVED | RESERVED | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R-000b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PD_MBIAS_FAULT1 | R/W | 0b | Powerdown configuration of MICBIAS fault 1
0d = No powerdown when MICBIAS fault detected 1d = MICBIAS and all ADC channels gets powerdown when low current fault occurs and P0_R40, PD_ON_FLT_CFG = 1d 1d = MICBIAS and all ADC channels gets powerdown when high current fault occurs and P0_R40, PD_ON_FLT_CFG = 2d |
| 6 | PD_MBIAS_FAULT2 | R/W | 0b | Powerdown configuration of MICBIAS fault 2
0d = No powerdown when MICBIAS fault detected 1d = MICBIAS and all ADC channels gets powerdown when over voltage fault occurs and P0_R40, PD_ON_FLT_CFG = 1d 1d = MICBIAS and all ADC channels gets powerdown when low current fault occurs and P0_R40, PD_ON_FLT_CFG = 2d |
| 5 | PD_MBIAS_FAULT3 | R/W | 0b | Powerdown configuration of MICBIAS fault 3
0d = No powerdown when MICBIAS fault detected 1d = MICBIAS and all ADC channels gets powerdown when over temperature fault occurs and P0_R40, PD_ON_FLT_CFG = 1d 1d = MICBIAS and all ADC channels gets powerdown when over voltage fault occurs and P0_R40, PD_ON_FLT_CFG = 2d |
| 4 | PD_MBIAS_FAULT4 | R/W | 1b | Powerdown configuration of MICBIAS fault 4
0d = No powerdown when MICBIAS fault detected 1d = MICBIAS and all ADC channels gets powerdown when high current fault occurs and P0_R40, PD_ON_FLT_CFG = 1d 1d = MICBIAS and all ADC channels gets powerdown when over temperature fault occurs and P0_R40, PD_ON_FLT_CFG = 2d. It is recommended to use this setting to protect chip from over temperature fault. |
| 3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 2-0 | RESERVED | R | 000b | Reserved bits; Write only reset value |
BIAS_CFG is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_BIAS_CFG_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_BIAS_CFG_TABLE.
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This register is the MICBIAS configuration register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MBIAS_VAL[3:0] | RESERVED | RESERVED | |||||
| R/W-1101b | R-00b | R/W-00b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | MBIAS_VAL[3:0] | R/W | 1101b | MICBIAS value.
Dont use Dont use Dont use Dont use Dont use Dont use Dont use 7d = Microphone bias is set to 5 V 8d = Microphone bias is set to 5.5 V 9d = Microphone bias is set to 6 V 10d = Microphone bias is set to 6.5 V 11d = Microphone bias is set to 7 V 12d = Microphone bias is set to 7.5 V 13d = Microphone bias is set to 8 V 14d = Microphone bias is set to 8.5 V 15d = Microphone bias is set to 9 V |
| 3-2 | RESERVED | R | 00b | Reserved bits; Write only reset value |
| 1-0 | RESERVED | R/W | 00b | Reserved bits; Write only reset values |
CH1_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG0_TABLE.
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This register is configuration register 0 for channel 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_INTYP | CH1_INSRC[1:0] | CH1_DC | CH1_MIC_IN_RANGE | CH1_PGA_CFG[1:0] | CH1_AGCEN | ||
| R/W-0b | R/W-00b | R/W-1b | R/W-0b | R/W-00b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CH1_INTYP | R/W | 0b | Channel 1 input type.
0d = Microphone input 1d = Line input |
| 6-5 | CH1_INSRC[1:0] | R/W | 00b | Channel 1 input configuration.
0d = Analog differential input 1d = Analog single-ended input 2d = Reserved 3d = Reserved |
| 4 | CH1_DC | R/W | 1b | Channel 1 input coupling.
0d = AC-coupled input 1d = DC-coupled input |
| 3 | CH1_MIC_IN_RANGE | R/W | 0b | Channel 1 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS supported provided DC differential common mode voltage IN1P - IN1M < 4.2 V. Single-ended AC signal 1-VRMS supported provided DC common mode voltage is < 2.1 V. 1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to 14.14 V or single ended 7.07 V supported. User rquired to adjust the channel gain and digital volume control based on the max signal level used in system. |
| 2-1 | CH1_PGA_CFG[1:0] | R/W | 00b | Channel 1 CMRR Configuration.
0d = High SNR performance mode Dont use 2d = High CMRR performance mode 3d = Reserved |
| 0 | CH1_AGCEN | R/W | 0b | Channel 1 automatic gain controller (AGC) setting.
0d = AGC disabled 1d = AGC enabled based on the configuration of bit 3 in register 108 (P0_R108); This must be used only with AC-coupled input |
CH1_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG1_TABLE.
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This register is configuration register 1 for channel 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_GAIN[5:0] | RESERVED | RESERVED | |||||
| R/W-000000b | R/W-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | CH1_GAIN[5:0] | R/W | 000000b | Channel 1 gain.
0d = Channel gain is set to 0 dB 1d = Channel gain is set to 1 dB 2d = Channel gain is set to 2 dB 3d to 41d = Channel gain is set as per configuration 42d = Channel gain is set to 42 dB 43d to 63d = Reserved |
| 1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CH1_CFG2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG2_TABLE.
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This register is configuration register 2 for channel 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_DVOL[7:0] | |||||||
| R/W-11001001b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CH1_DVOL[7:0] | R/W | 11001001b | Channel 1 digital volume control.
0d = Digital volume is muted 1d = Digital volume control is set to -100 dB 2d = Digital volume control is set to -99.5 dB 3d to 200d = Digital volume control is set as per configuration 201d = Digital volume control is set to 0 dB 202d = Digital volume control is set to 0.5 dB 203d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 26.5 dB 255d = Digital volume control is set to 27 dB |
CH1_CFG3 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG3_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG3_TABLE.
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This register is configuration register 3 for channel 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_GCAL[3:0] | RESERVED | ||||||
| R/W-1000b | R-0000b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | CH1_GCAL[3:0] | R/W | 1000b | Channel 1 gain calibration.
0d = Gain calibration is set to -0.8 dB 1d = Gain calibration is set to -0.7 dB 2d = Gain calibration is set to -0.6 dB 3d to 7d = Gain calibration is set as per configuration 8d = Gain calibration is set to 0 dB 9d = Gain calibration is set to 0.1 dB 10d to 13d = Gain calibration is set as per configuration 14d = Gain calibration is set to 0.6 dB 15d = Gain calibration is set to 0.7 dB |
| 3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
CH1_CFG4 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG4_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH1_CFG4_TABLE.
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This register is configuration register 4 for channel 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_PCAL[7:0] | |||||||
| R/W-00000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CH1_PCAL[7:0] | R/W | 00000000b | Channel 1 phase calibration with modulator clock resolution.
0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 254d = Phase calibration delay as per configuration 255d = Phase calibration delay is set to 255 cycles of the modulator clock |
CH2_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG0_TABLE.
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This register is configuration register 0 for channel 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH2_INTYP | CH2_INSRC[1:0] | CH2_DC | CH2_MIC_IN_RANGE | CH2_PGA_CFG[1:0] | CH2_AGCEN | ||
| R/W-0b | R/W-00b | R/W-1b | R/W-0b | R/W-00b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CH2_INTYP | R/W | 0b | Channel 2 input type.
0d = Microphone input 1d = Line input |
| 6-5 | CH2_INSRC[1:0] | R/W | 00b | Channel 2 input configuration.
0d = Analog differential input 1d = Analog single-ended input 2d = Reserved 3d = Reserved |
| 4 | CH2_DC | R/W | 1b | Channel 2 input coupling.
0d = AC-coupled input 1d = DC-coupled input |
| 3 | CH2_MIC_IN_RANGE | R/W | 0b | Channel 2 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS supported provided DC differential common mode voltage IN1P - IN1M < 4.2 V. Single-ended AC signal 1-VRMS supported provided DC common mode voltage is < 2.1 V. 1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to 14.14 V or single ended 7.07 V supported. User rquired to adjust the channel gain and digital volume control based on the max signal level used in system. |
| 2-1 | CH2_PGA_CFG[1:0] | R/W | 00b | Channel 2 CMRR Configuration.
0d = High SNR performance mode Dont use 2d = High CMRR performance mode 3d = Reserved |
| 0 | CH2_AGCEN | R/W | 0b | Channel 2 automatic gain controller (AGC) setting.
0d = AGC disabled 1d = AGC enabled based on the configuration of bit 3 in register 108 (P0_R108); This must be used only with AC-coupled input |
CH2_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG1_TABLE.
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This register is configuration register 1 for channel 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH2_GAIN[5:0] | RESERVED | RESERVED | |||||
| R/W-000000b | R/W-0b | R-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | CH2_GAIN[5:0] | R/W | 000000b | Channel 2 gain.
0d = Channel gain is set to 0 dB 1d = Channel gain is set to 1 dB 2d = Channel gain is set to 2 dB 3d to 41d = Channel gain is set as per configuration 42d = Channel gain is set to 42 dB 43d to 63d = Reserved |
| 1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CH2_CFG2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG2_TABLE.
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This register is configuration register 2 for channel 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH2_DVOL[7:0] | |||||||
| R/W-11001001b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CH2_DVOL[7:0] | R/W | 11001001b | Channel 2 digital volume control.
0d = Digital volume is muted 1d = Digital volume control is set to -100 dB 2d = Digital volume control is set to -99.5 dB 3d to 200d = Digital volume control is set as per configuration 201d = Digital volume control is set to 0 dB 202d = Digital volume control is set to 0.5 dB 203d to 253d = Digital volume control is set as per configuration 254d = Digital volume control is set to 26.5 dB 255d = Digital volume control is set to 27 dB |
CH2_CFG3 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG3_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG3_TABLE.
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This register is configuration register 3 for channel 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH2_GCAL[3:0] | RESERVED | ||||||
| R/W-1000b | R-0000b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | CH2_GCAL[3:0] | R/W | 1000b | Channel 2 gain calibration.
0d = Gain calibration is set to -0.8 dB 1d = Gain calibration is set to -0.7 dB 2d = Gain calibration is set to -0.6 dB 3d to 7d = Gain calibration is set as per configuration 8d = Gain calibration is set to 0 dB 9d = Gain calibration is set to 0.1 dB 10d to 13d = Gain calibration is set as per configuration 14d = Gain calibration is set to 0.6 dB 15d = Gain calibration is set to 0.7 dB |
| 3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
CH2_CFG4 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG4_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_CH2_CFG4_TABLE.
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This register is configuration register 4 for channel 2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH2_PCAL[7:0] | |||||||
| R/W-00000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CH2_PCAL[7:0] | R/W | 00000000b | Channel 2 phase calibration with modulator clock resolution.
0d = No phase calibration 1d = Phase calibration delay is set to one cycle of the modulator clock 2d = Phase calibration delay is set to two cycles of the modulator clock 3d to 254d = Phase calibration delay as per configuration 255d = Phase calibration delay is set to 255 cycles of the modulator clock |
DIAG_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG0_TABLE.
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This register is configuration register 0 for input fault diagnostics setting.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_DIAG_EN | CH2_DIAG_EN | RESERVED | RESERVED | RESERVED | RESERVED | INCL_SE_INM | INCL_AC_COUP |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CH1_DIAG_EN | R/W | 0b | Channel 1 input (IN1P and IN1M) scan for diagnostics.
0d = Diagnostic disabled 1d = Diagnostic enabled |
| 6 | CH2_DIAG_EN | R/W | 0b | Channel 2 input (IN2P and IN2M) scan for diagnostics.
0d = Diagnostic disabled 1d = Diagnostic enabled |
| 5 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 1 | INCL_SE_INM | R/W | 0b | INxM pin diagnostics scan selection for single-ended configuration.
0d = INxM pins of single-ended channels are excluded for diagnosis 1d = INxM pins of single-ended channels are included for diagnosis |
| 0 | INCL_AC_COUP | R/W | 0b | AC-coupled channels pins scan selection for diagnostics.
0d = INxP and INxM pins of AC-coupled channels are excluded for diagnosis 1d = INxP and INxM pins of AC-coupled channels are included for diagnosis |
DIAG_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG1_TABLE.
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This register is configuration register 1 for input fault diagnostics setting.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DIAG_SHT_TERM[3:0] | DIAG_SHT_VBAT_IN[3:0] | ||||||
| R/W-0011b | R/W-0111b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | DIAG_SHT_TERM[3:0] | R/W | 0011b | INxP and INxM terminal short detect threshold.
0d = INxP and INxM terminal short detect threshold value is 0 mV (typ) 1d = INxP and INxM terminal short detect threshold value is 30 mV (typ) 2d = INxP and INxM terminal short detect threshold value is 60 mV (typ) 10d to 13d = INxP and INxM terminal short detect threshold value is set as per configuration 14d = INxP and INxM terminal short detect threshold value is 420 mV (typ) 15d = INxP and INxM terminal short detect threshold value is 450 mV (typ) |
| 3-0 | DIAG_SHT_VBAT_IN[3:0] | R/W | 0111b | Short to VBAT_IN detect threshold.
0d = Short to VBAT_IN detect threshold value is 0 mV (typ) 1d = Short to VBAT_IN detect threshold value is 30 mV (typ) 2d = Short to VBAT_IN detect threshold value is 60 mV (typ) 10d to 13d = Short to VBAT_IN detect threshold value is set as per configuration 14d = Short to VBAT_IN detect threshold value is 420 mV (typ) 15d = Short to VBAT_IN detect threshold value is 450 mV (typ) |
DIAG_CFG2 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG2_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG2_TABLE.
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This register is configuration register 2 for input fault diagnostics setting.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DIAG_SHT_GND[3:0] | DIAG_SHT_MICBIAS[3:0] | ||||||
| R/W-1000b | R/W-0111b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | DIAG_SHT_GND[3:0] | R/W | 1000b | Short to ground detect threshold.
0d = Short to ground detect threshold value is 0 mV (typ) 1d = Short to ground detect threshold value is 60 mV (typ) 2d = Short to ground detect threshold value is 120 mV (typ) 10d to 13d = Short to ground detect threshold value is set as per configuration 14d = Short to ground detect threshold value is 840 mV (typ) 15d = Short to ground detect threshold value is 900 mV (typ) |
| 3-0 | DIAG_SHT_MICBIAS[3:0] | R/W | 0111b | Short to MICBIAS detect threshold.
0d = Short to MICBIAS detect threshold value is 0 mV (typ) 1d = Short to MICBIAS detect threshold value is 30 mV (typ) 2d = Short to MICBIAS detect threshold value is 60 mV (typ) 10d to 13d = Short to MICBIAS detect threshold value is set as per configuration 14d = Short to MICBIAS detect threshold value is 420 mV (typ) 15d = Short to MICBIAS detect threshold value is 450 mV (typ) |
DIAG_CFG3 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG3_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG3_TABLE.
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This register is configuration register 3 for input fault diagnostics setting.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REP_RATE[1:0] | RESERVED | FAULT_DBNCE_SEL[1:0] | VSHORT_DBNCE | DIAG_2X_THRES | |||
| R/W-10b | R/W-11b | R/W-10b | R/W-0b | R/W-0b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | REP_RATE[1:0] | R/W | 10b | Fault monitoring scan repetition rate.
0d = Countinuos back to back scanning of selected channels input pins without any idle time 1d = Fault monitoring repetition rate of 1 ms for selected channels input pins scanning 2d = Fault monitoring repetition rate of 4 ms for selected channels input pins scanning 3d = Fault monitoring repetition rate of 8 ms for selected channels input pins scanning |
| 5-4 | RESERVED | R/W | 11b | Reserved bits; Write only reset values |
| 3-2 | FAULT_DBNCE_SEL[1:0] | R/W | 10b | Debounce count for all the faults (except VBAT_IN short when VBAT_IN < MICBIAS).
0d = 16 counts for debounce to filter-out any false faults detection 1d = 8 counts for debounce to filter-out any false faults detection 2d = 4 counts for debounce to filter-out any false faults detection 3d = No debounce count |
| 1 | VSHORT_DBNCE | R/W | 0b | VBAT_IN short debounce count only when VBAT_IN < MICBIAS.
0d = 16 counts for debounce to filter-out any false faults detection 1d = 8 counts for debounce to filter-out any false faults detection |
| 0 | DIAG_2X_THRES | R/W | 0b | Diagnostic thresholds range scale.
0d = Thresholds same as configured in P0_R101 and P0_R102 1d = All the configuration thresholds gets scale by 2 times |
DIAG_CFG4 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG4_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DIAG_CFG4_TABLE.
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This register is configuration register 4 for input fault diagnostics setting.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DIAG_MOV_AVG_CFG[1:0] | MOV_AVG_DIS_MBIAS_LOAD | MOV_AVG_DIS_TEMP_SENS | RESERVED | ||||
| R/W-00b | R/W-0b | R/W-0b | R-0000b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | DIAG_MOV_AVG_CFG[1:0] | R/W | 00b | Moving average configuration.
0d = Moving average disabled 1d = Moving average enabled with 0.5 weightage for old scanned data and new scanned data 2d = Moving average enabled with 0.75 weightage for old scanned data and 0.25 weightage for new scanned data 3d = Reserved |
| 5 | MOV_AVG_DIS_MBIAS_LOAD | R/W | 0b | Moving average configuration for MICBIAS high and low load current fault detection
0d = Moving average as defined by DIAG_MOV_AVG_CFG setting 1d = Moving average is forced disabled for MICBIAS load current fault detection to achieve faster response time |
| 4 | MOV_AVG_DIS_TEMP_SENS | R/W | 0b | Moving average configuration for over temperature fault detection
0d = Moving average as defined by DIAG_MOV_AVG_CFG setting 1d = Moving average is forced disabled for over temperature fault detection to achieve faster response time |
| 3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset values |
BOOST_CFG is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_BOOST_CFG_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_BOOST_CFG_TABLE.
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This register is configuration register for boost setting.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BOOST_DIS | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-000b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BOOST_DIS | R/W | 0b | Boost Enable/Disable
0d = Boost is enable 1d = Boost is disable/bypass |
| 6 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 5 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 2-0 | RESERVED | R | 000b | Reserved bits; Write only reset values |
DSP_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DSP_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DSP_CFG0_TABLE.
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This register is the digital signal processor (DSP) configuration register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DECI_FILT[1:0] | CH_SUM[1:0] | HPF_SEL[1:0] | ||||
| R-00b | R/W-00b | R/W-00b | R/W-01b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | Reserved bits; Write only reset value |
| 5-4 | DECI_FILT[1:0] | R/W | 00b | Decimation filter response.
0d = Linear phase 1d = Low latency 2d = Ultra-low latency Dont use |
| 3-2 | CH_SUM[1:0] | R/W | 00b | Channel summation mode for higher SNR
0d = Channel summation mode is disabled 1d = 2-channel summation mode is enabled to generate a (CH1 + CH2) / 2 2d = Reserved 3d = Reserved |
| 1-0 | HPF_SEL[1:0] | R/W | 01b | High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P4_R72 to P4_R83 set as the all-pass filter 1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is selected 2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected 3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is selected |
DSP_CFG1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DSP_CFG1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DSP_CFG1_TABLE.
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This register is the digital signal processor (DSP) configuration register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DVOL_GANG | BIQUAD_CFG[1:0] | DISABLE_SOFT_STEP | AGC_SEL | RESERVED | RESERVED | ||
| R/W-0b | R/W-10b | R/W-0b | R/W-1b | R/W-0b | R-00b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DVOL_GANG | R/W | 0b | DVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed in the CHx_DVOL bits 1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL) irrespective of whether channel 1 is turned on or not |
| 6-5 | BIQUAD_CFG[1:0] | R/W | 10b | Number of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled 1d = 1 biquad per channel 2d = 2 biquads per channel 3d = 3 biquads per channel |
| 4 | DISABLE_SOFT_STEP | R/W | 0b | Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled 1d = Soft-stepping disabled |
| 3 | AGC_SEL | R/W | 1b | AGC master enable setting.
0d = Reserved; Write always 1 to this register bit 1d = AGC selected as configured for each channel using CHx_CFG0 register |
| 2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 1-0 | RESERVED | R | 00b | Reserved bits; Write only reset value |
AGC_CFG0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_AGC_CFG0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_AGC_CFG0_TABLE.
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This register is the automatic gain controller (AGC) configuration register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AGC_LVL[3:0] | AGC_MAXGAIN[3:0] | ||||||
| R/W-1110b | R/W-0111b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | AGC_LVL[3:0] | R/W | 1110b | AGC output signal target level.
0d = Output signal target level is -6 dB 1d = Output signal target level is -8 dB 2d = Output signal target level is -10 dB 3d to 13d = Output signal target level is as per configuration 14d = Output signal target level is -34 dB 15d = Output signal target level is -36 dB |
| 3-0 | AGC_MAXGAIN[3:0] | R/W | 0111b | AGC maximum gain allowed.
0d = Maximum gain allowed is 3 dB 1d = Maximum gain allowed is 6 dB 2d = Maximum gain allowed is 9 dB 3d to 11d = Maximum gain allowed is as per configuration 12d = Maximum gain allowed is 39 dB 13d = Maximum gain allowed is 42 dB 14d to 15d = Reserved |
IN_CH_EN is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_IN_CH_EN_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_IN_CH_EN_TABLE.
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This register is the input channel enable configuration register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IN_CH1_EN | IN_CH2_EN | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
| R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | IN_CH1_EN | R/W | 1b | Input channel 1 enable setting.
0d = Channel 1 is disabled 1d = Channel 1 is enabled |
| 6 | IN_CH2_EN | R/W | 1b | Input channel 2 enable setting.
0d = Channel 2 is disabled 1d = Channel 2 is enabled |
| 5 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 4 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 3 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 2 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
| 1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
ASI_OUT_CH_EN is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_OUT_CH_EN_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_ASI_OUT_CH_EN_TABLE.
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This register is the ASI output channel enable configuration register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ASI_OUT_CH1_EN | ASI_OUT_CH2_EN | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ASI_OUT_CH1_EN | R/W | 0b | ASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition 1d = Channel 1 output slot is enabled |
| 6 | ASI_OUT_CH2_EN | R/W | 0b | ASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition 1d = Channel 2 output slot is enabled |
| 5 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
PWR_CFG is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_PWR_CFG_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_PWR_CFG_TABLE.
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This register is the power-up configuration register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MICBIAS_PDZ | ADC_PDZ | PLL_PDZ | DYN_CH_PUPD_EN | RESERVED | RESERVED | RESERVED | |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-00b | R/W-0b | R-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | MICBIAS_PDZ | R/W | 0b | Power control for MICBIAS.
0d = Power down MICBIAS 1d = Power up MICBIAS |
| 6 | ADC_PDZ | R/W | 0b | Power control for ADC and PDM channels.
0d = Power down all ADC and PDM channels 1d = Power up all enabled ADC and PDM channels |
| 5 | PLL_PDZ | R/W | 0b | Power control for the PLL.
0d = Power down the PLL 1d = Power up the PLL |
| 4 | DYN_CH_PUPD_EN | R/W | 0b | Dynamic channel power-up, power-down enable.
0d = Channel power-up, power-down is not supported if any channel recording is on 1d = Channel can be powered up or down individually, even if channel recording is on. Do not powered-down channel 1 if this bit is set to '1' |
| 3-2 | RESERVED | R/W | 00b | Reserved bits; Write only reset values |
| 1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
| 0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
DEV_STS0 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DEV_STS0_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DEV_STS0_TABLE.
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This register is the device status value register 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH1_STATUS | CH2_STATUS | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | CH1_STATUS | R | 0b | ADC channel 1 power status.
0d = ADC channel is powered down 1d = ADC channel is powered up |
| 6 | CH2_STATUS | R | 0b | ADC channel 2 power status.
0d = ADC channel is powered down 1d = ADC channel is powered up |
| 5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
| 0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
DEV_STS1 is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DEV_STS1_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_DEV_STS1_TABLE.
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This register is the device status value register 1.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MODE_STS[2:0] | BOOST_STS | MBIAS_STS | CHx_PD_FLT_STS | ALL_CHx_PD_FLT_STS | MAN_RCV_PD_FLT_CHK | ||
| R-100b | R-0b | R-0b | R-0b | R-0b | R/W-0b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | MODE_STS[2:0] | R | 100b | Device mode status.
4d = Device is in sleep mode or software shutdown mode 6d = Device is in active mode with all ADC or PDM channels turned off 7d = Device is in active mode with at least one ADC or PDM channel turned on |
| 4 | BOOST_STS | R | 0b | Boost power up status.
0d = Boost is powered down 1d = Boost is powered up |
| 3 | MBIAS_STS | R | 0b | MICBIAS power up status.
0d = MICBIAS is powered down 1d = MICBIAS is powered up |
| 2 | CHx_PD_FLT_STS | R | 0b | ADC channel power down status caused by INxx inputs faults.
0d = No ADC channel is powered down caused by INxx inputs faults 1d = Atleast a ADC channel is powered down caused by INxx inputs faults |
| 1 | ALL_CHx_PD_FLT_STS | R | 0b | ADC channel power down status caused by MICBIAS faults.
0d = No ADC channel is powered down caused by MICBIAS faults 1d = All ADC channels are powered down caused by MICBIAS faults |
| 0 | MAN_RCV_PD_FLT_CHK | R/W | 0b | Manual recovery (self-clearing bit).
0d = No effect 1d = Recheck all fault status and re-powerup ADC channels and/or MICBIAS if they do not have any faults. Before setting this bit, reset P0_R58 register and re-configure P0_R58 to desired setting only after manual recover gets over. |
I2C_CKSUM is shown in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_I2C_CKSUM_FIGURE and described in GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#PCM6020_PAGE_0_PAGE_0_I2C_CKSUM_TABLE.
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This register returns the I2C transactions checksum value
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| I2C_CKSUM[7:0] | |||||||
| R/W-00000000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | I2C_CKSUM[7:0] | R/W | 00000000b | These bits return the I2C transactions checksum value. Writing to this register resets the checksum to the written value. This register is updated on writes to other registers on all pages. |