SBASA12 December   2020 PCM6020-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3 Input Channel Configuration
      4. 8.3.4 Reference Voltage
      5. 8.3.5 Microphone Bias
      6. 8.3.6 Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.7.2 Programmable Channel Gain Calibration
        3. 8.3.7.3 Programmable Channel Phase Calibration
        4. 8.3.7.4 Programmable Digital High-Pass Filter
        5. 8.3.7.5 Programmable Digital Biquad Filters
        6. 8.3.7.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.7.7 Configurable Digital Decimation Filters
          1. 8.3.7.7.1 Linear Phase Filters
            1. 8.3.7.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.7.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.7.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.7.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.7.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.7.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.7.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.7.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.7.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.7.7.2 Low-Latency Filters
            1. 8.3.7.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.7.7.3 Ultra-Low-Latency Filters
            1. 8.3.7.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.7.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      8. 8.3.8 Automatic Gain Controller (AGC)
      9. 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Registers Access Type
        2. 8.6.1.2 Page 0 Registers
        3. 8.6.1.3 Page 1 Registers
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page 2
        2. 8.6.2.2 Programmable Coefficient Registers: Page 3
        3. 8.6.2.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 2-Channel Analog Microphone Recording Using the PCM6020-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the PCM6020-Q1 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S or left-justified protocols format, programmable data length options, very flexible master-slave configurability for bus clock lines, and the ability to communicate with multiple devices within a system directly.

The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0], P0_R7_D[7:6] register bits. As shown in Table 8-2 and Table 8-3, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16, 20, 24, or 32 bits by configuring the ASI_WLEN[1:0], P0_R7_D[5:4] register bits.

Table 8-2 Audio Serial Interface Format
P0_R7_D[7:6] : ASI_FORMAT[1:0]AUDIO SERIAL INTERFACE FORMAT
00 (default)Time division multiplexing (TDM) mode
01Inter IC sound (I2S) mode
10Left-justified (LJ) mode
11Reserved (do not use this setting)
Table 8-3 Audio Output Channel Data Word-Length
P0_R7_D[5:4] : ASI_WLEN[1:0]AUDIO OUTPUT CHANNEL DATA WORD-LENGTH
00Output channel data word-length set to 16 bits
01Output channel data word-length set to 20 bits
10Output channel data word-length set to 24 bits
11 (default)Output channel data word-length set to 32 bits

The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio data across the serial bus. The number of bit clock cycles in a frame must accommodate multiple device active output channels with the programmed data word length.

A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data transmissions to complete on the audio bus by a device or multiple PCM6020-Q1 devices sharing the same audio bus. The device supports up to two output channels that can be configured to place their audio data on bus slot 0 to slot 63. Table 8-4 lists the output channel slot configuration settings. In I2S and LJ mode, the slots are divided into two sets, left-channel slots and right-channel slots, as described in the Section 8.3.1.2.2 and Section 8.3.1.2.3 sections.

Table 8-4 Output Channel Slot Assignment Settings
P0_R11_D[5:0] : CH1_SLOT[5:0]OUTPUT CHANNEL 1 SLOT ASSIGNMENT
00 0000 = 0d (default)Slot 0 for TDM or left slot 0 for I2S, LJ.
00 0001 = 1dSlot 1 for TDM or left slot 1 for I2S, LJ.
……
01 1111 = 31dSlot 31 for TDM or left slot 31 for I2S, LJ.
10 0000 = 32dSlot 32 for TDM or right slot 0 for I2S, LJ.
……
11 1110 = 62dSlot 62 for TDM or right slot 30 for I2S, LJ.
11 1111 = 63dSlot 63 for TDM or right slot 31 for I2S, LJ.

Similarly, the slot assignment setting for output channel 2 can be done using the CH2_SLOT (P0_R12) register.

The slot word length is the same as the output channel data word length set for the device. The output channel data word length must be set to the same value for all PCM6020-Q1 devices if all devices share the same ASI bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data word length configured.

The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by up to 31 cycles of the bit clock. Table 8-5 lists the programmable offset configuration settings.

Table 8-5 Programmable Offset Settings for the ASI Slot Start
P0_R8_D[4:0] : TX_OFFSET[4:0]PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START
0 0000 = 0d (default)The device follows the standard protocol timing without any offset.
0 0001 = 1dSlot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to standard protocol timing.
............
1 1110 = 30dSlot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
1 1111 = 31dSlot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.

The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using the FSYNC_POL, P0_R7_D3 register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK, which can be set using the BCLK_POL, P0_R7_D2 register bit.