SLLSEB3C March   2012  – November 2016 SN65LVPE502A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
      1. 6.7.1 Case I - Fixed Output, Variable Input Trace, and 3-m Cable
      2. 6.7.2 Case II - Fixed Input, Variable Output Trace, and 3-m Cable
      3. 6.7.3 Case III - Fixed Input and Variable Output Trace (No Cable)
  7. Parameter Measurement Information
    1. 7.1 Typical Eye Diagram and Performance Curves
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Host- and Device-Side Pins
      2. 8.3.2 Programmable EQ, De-Emphasis and Amplitude Swing
      3. 8.3.3 Receiver Detection
        1. At Power Up or Reset
        2. During U2/U3 Link State
      4. 8.3.4 Electrical Idle Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Modes
        1. Sleep Mode
        2. RX Detect Mode
        3. U2/U3 Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

One example of the SN65LVPE502x used in a Host application on transmit and receive channels is shown in Typical Application. The redriver is required on the PCB path to pass transmitter compliance due to loss between the Host and connector. The redriver uses its equalization to recover the insertion loss and re-drive the signal with boosted swing down the remaining channel, through the USB 3.0 cable, and into the device PCB. Additionally on the receiver path, the SN65LVPE502x compensated for the Host to pass receiver jitter tolerance. The redriver recovers the loss from the device PCB, connector, and USB 3.0 cable and redrives the signal going into the Host receiver. The equalization, output swing, and de-emphasis settings are dependent upon the type of USB 3.0 signal path and end application.

Typical Application

SN65LVPE502A SN65LVPE502B typ_app_dia_llse79.gif Figure 31. Typical Application Schematic

Design Requirements

Table 6 lists the parameters for this example.

Table 6. Application Parameters

Input voltage range 100 mV to 1200 mV
Output voltage range 1050 mV to 1200 mV
Equalization 0, 7, 15 bD (2.5 Gbps)
De-emphasis 0, –3, –5 dB (OS floating)
VCC 3.3-V nominal supply

Detailed Design Procedure

The SN65LVPE502x is placed in the Host side and connected to a USB3 Type-A connector. The EQ and DE terminals must be pulled up, pulled down, or left floating depending on the amount of equalization or de-emphasis that is desired. The OS terminal must be pulled down or left floating depending on the required output swing. This device has terminals to be exclusively connected to the Host and to the device accordingly. In this Host side (even though the RX and TX pairs must be AC-coupled), this is an embedded implementation and Figure 31 only shows the AC-coupling capacitors on the TX pair to follow the convention.

To begin the design process, determine the following:

  • Equalization (EQ) setting
  • De-emphasis (DE) setting
  • Output swing amplitude (OS) setting

The equalization must be set based on the insertion loss in the pre-channel (channel before the SN65LVPE502x device). The input voltage to the device is able to have a large range because of the receiver sensitivity and the available EQ settings. The EQ terminal can be pulled high through a resistor to VCC, low through a resistor to ground, or left floating. The de-emphasis setting must be set based on the length and characteristics of the post channel (channel after the SN65LVPE502x device). Output de-emphasis can be tailored using the DE terminal. This terminal must be pulled high through a resistor to VCC, low through a resistor to ground, or left floating. The output swing setting can also be configured based on the amplitude requirement to pass the compliance test. This setting is also based on the length of interconnect or cable the SN65LVPE502x is driving. This terminal must be pulled low through a resistor to ground or left floating.

Application Curves

SN65LVPE502A SN65LVPE502B scope_image_02_llseb3.gif
Measured at device end with DE = 0 dB, EQ = 0 dB,
pre-channel = 20 in., and post-channel = 4 in. plus 3-m cable
Figure 32. Eye-Mask Measured at the Device End
With No Equalization
SN65LVPE502A SN65LVPE502B scope_image_01_llseb3.gif
Measured at device end with DE = 0 dB, EQ = 7 dB,
pre-channel = 20 in., and post-channel = 4 in. plus 3-m cable
Figure 33. Eye-Mask With 7-dB Equalization