SLLSEB3C March   2012  – November 2016 SN65LVPE502A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
      1. 6.7.1 Case I - Fixed Output, Variable Input Trace, and 3-m Cable
      2. 6.7.2 Case II - Fixed Input, Variable Output Trace, and 3-m Cable
      3. 6.7.3 Case III - Fixed Input and Variable Output Trace (No Cable)
  7. 7 Parameter Measurement Information
    1. 7.1 Typical Eye Diagram and Performance Curves
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Host- and Device-Side Pins
      2. 8.3.2 Programmable EQ, De-Emphasis and Amplitude Swing
      3. 8.3.3 Receiver Detection
        1. 8.3.3.1 At Power Up or Reset
        2. 8.3.3.2 During U2/U3 Link State
      4. 8.3.4 Electrical Idle Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Modes
        1. 8.4.2.1 Sleep Mode
        2. 8.4.2.2 RX Detect Mode
        3. 8.4.2.3 U2/U3 Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

SN65LVPE502A RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
SN65LVPE502A SN65LVPE502B po_502A_llseb3.gif
SN65LVPE502B RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
SN65LVPE502A SN65LVPE502B po_502B_llseb3.gif

Pin Functions – RGE Packages

PIN TYPE(1) DESCRIPTION
NAME SN65LVPE502A SN65LVPE502B
HIGH SPEED DIFFERENTIAL I/O PINS
Host_RX1– 8 20 I CML, inverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side.
Host_RX1+ 9 19 I CML, noninverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side.
Device_RX2– 20 8 I CML, inverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side.
Device_RX2+ 19 9 I CML, noninverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side.
Device_TX1– 23 11 O CML, inverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side.
Device_TX1+ 22 12 O CML, noninverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side.
Host_TX2– 11 23 O CML, inverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side.
Host_TX2+ 12 22 O CML, noninverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side.
DEVICE CONTROL PINS
EN_RXD 5 17 I LVCMOS, sets device operation modes per Table 4; internally pulled to VCC.
RSVD 14 — I LVCMOS; RSVD. Can be left as No-Connect.
NC 7, 24 2, 3, 4, 6, 14, 18, 24 — Pads are not internally connected.
EQ CONTROL PINS(2)
DE1, DE2 3, 16 16, 5 I LVCMOS, selects de-emphasis settings for CH1 and CH2 per Table 4; internally tied to VCC/2.
EQ1, EQ2 2, 17 15, 7 I LVCMOS, selects equalization settings for CH1 and CH2 per Table 4, internally tied to VCC/2.
OS1, OS2 4, 15 — I LVCMOS, selects output amplitude for CH1 and CH2 per Table 4, internally tied to VCC/2.
POWER PINS(3)
GND 6, 10, 18, 21, Thermal Pad 10, 21, Thermal Pad P Supply ground
VCC 1,13 1, 13 P Positive supply; must be 3.3 V ±10%
(1) I = Input, O = Output, P = Power
(2) Internally biased to VCC/2 with >200 kΩ pullup or pulldown. When pins are left as NC, board leakage at this pin pad must be <1 µA otherwise drive to Vcc/2 to assert mid-level state.
(3) For SN65LVPE502B, pins 10 and 21 must be connected to GND, while 6 and 18 may be NC. For SN65LVPE502A, TI recommends at least two of the four pins (6, 10, 18, 21) be connected to ground.
SN65LVPE502A RLL Package
24-Pin VQFN With Exposed Thermal Pad
Top View
SN65LVPE502A SN65LVPE502B RLL.gif

Pin Functions – RLL Package

PIN TYPE(1) DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/O PINS
Host_RX1– 19 I CML, inverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side.
Host_RX1+ 20 I CML, noninverting differential input for CH1. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 host side.
Device_RX2– 8 I CML, inverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side.
Device_RX2+ 7 I CML, noninverting differential input for CH2. This pin is tied to an internal voltage bias by dual termination resistor circuit. Must connect to the USB 3.0 Device side.
Device_TX1– 11 O CML, inverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side.
Device_TX1+ 10 O CML, noninverting differential output for CH1. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Device side.
Host_TX2– 22 O CML, inverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side.
Host_TX2+ 23 O CML, noninverting differential output for CH2. This pin is tied to an internal voltage bias by termination resistors. Must connect to the USB 3.0 Host side.
DEVICE CONTROL PINS
EN_RXD 17 I LVCMOS, sets device operation modes per Table 4; internally pulled to VCC.
NC 1, 2, 6, 12, 18, 24 — Pads are not internally connected.
EQ CONTROL PINS(2)
DE1, DE2 15, 4 I LVCMOS, selects de-emphasis settings for CH1 and CH2 per Table 4; internally tied to VCC/2.
EQ1, EQ2 14, 5 I LVCMOS, selects equalization settings for CH1 and CH2 per Table 4; internally tied to VCC/2.
OS1, OS2 16, NC(3) I LVCMOS, selects output amplitude for CH1 and CH2 per Table 4; internally tied to VCC/2.
POWER PINS
GND 9, Thermal Pad P Supply ground
VCC 3 P Positive supply; must be 3.3 V ±10%
(1) I = Input, O = Output, P = Power
(2) Internally biased to VCC/2 with >200 kΩ pullup or pulldown. When pins are left as NC, board leakage at this pin pad must be <1 µA otherwise drive to Vcc/2 to assert mid-level state.
(3) The SN65LVPE502A RLL package has OS2 internal no-connect to select the 1042-mVpp level on TX2.