SLLSEB3C March   2012  – November 2016 SN65LVPE502A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
      1. 6.7.1 Case I - Fixed Output, Variable Input Trace, and 3-m Cable
      2. 6.7.2 Case II - Fixed Input, Variable Output Trace, and 3-m Cable
      3. 6.7.3 Case III - Fixed Input and Variable Output Trace (No Cable)
  7. Parameter Measurement Information
    1. 7.1 Typical Eye Diagram and Performance Curves
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Host- and Device-Side Pins
      2. 8.3.2 Programmable EQ, De-Emphasis and Amplitude Swing
      3. 8.3.3 Receiver Detection
        1. At Power Up or Reset
        2. During U2/U3 Link State
      4. 8.3.4 Electrical Idle Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Modes
        1. Sleep Mode
        2. RX Detect Mode
        3. U2/U3 Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


When 5-Gbps SuperSpeed USB signals travel across a PCB or cable, signal integrity degrades due to loss and inter-symbol interference (ISI). The SN65LVPE502x devices recover incoming data by applying equalization that compensates for channel loss, and drives out signals with a high differential voltage. This extends the possible channel length, and enables systems to pass USB 3.0 compliance. The SN65LVPE502x is located at the Host side. After power up, the SN65LVPE502x periodically performs receiver detection on the TX pair. If it detects a SuperSpeed USB receiver, the RX termination is enabled, and the SN65LVPE502x is ready to redrive. The receiver equalizer has three gain settings that are controlled by terminal EQ: 0 dB, 7 dB, and 15 dB. The equalization must be set based on amount of insertion loss in the channel before the SN65LVPE502x. Likewise, the output driver supports configuration of de-emphasis and output swing (terminals DE and OS).

Functional Block Diagram

SN65LVPE502A SN65LVPE502B data_flow_bd_llseb3.gif

Feature Description

Host- and Device-Side Pins

The SN65LVPE502x features a link state machine that makes the device transparent on the USB 3.0 bus while minimizing power. The state machine relies on the system host to be connected to the pins named Host. USB 3.0 devices must be connected to the pins named Device. Multiple SN65LVPE502x devices may be used in series.

Programmable EQ, De-Emphasis and Amplitude Swing

The SN65LVPE502x is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for any anticipated USB 3.0 signal distortion experienced. The level of de-emphasis depends on the length of interconnect and its characteristics. The SN65LVPE502x provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All RX and TX equalization settings supported by the device are programmed by six 3-state pins as shown in Table 4.

Table 4. Signal Control Pin Setting

NC (default) 1042 NC (default) 0
0 908 0 7
1 1127 1 15
DEx(1) OSx(1) = NC OSx(1) = 0 OSx(1) = 1
NC (default) 0 dB 0 dB 0 dB
0 –3.5 dB –2.2 dB –4.4 dB
1 –6 dB –5.2 dB –6 dB
Where x = Channel 1 or Channel 2

Receiver Detection

At Power Up or Reset

After power-up or anytime EN_RXD is toggled, RX.Detect cycle is performed by first setting RX termination for each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of each TX.

If the receiver is detected on both channel, the TX and RX terminations are switched to ZDIFF_TX, ZDIFF_RX respectively.

If no receiver is detected on one or both channels, the transmitter is pulled to Hi-Z; the channel is put in low-power mode; and the device attempts to detect RX termination in 12 ms (typical) interval until termination is found or device is put in sleep mode.

During U2/U3 Link State

RX detection is also performed periodically when link is in U2/U3 states. However in these states during RX detection, input termination is not automatically disabled before performing RX.Detect. If termination is found device goes back to its low power state if termination is not found then device disables its input termination and then jumps to power-up RX.Detect state.

Electrical Idle Support

Electrical idle support is required for low frequency periodic signaling (LFPS) used in USB 3.0 side band communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE502x detects an electrical idle state when RX± voltage at the device pin falls below VRX_LFPS_DIFFpp minimum. After detection of an idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VRX_LFPS_DIFFpp maximum normal operation is restored and output start passing input signal. Electrical idle exit and entry time is specified at <6 ns.

Device Functional Modes

Active Mode

This operating mode is enabled when EN_RXD is driven to VCC and the device has successfully detected the connection with Host and Device, the redriver applies the desired equalization to the inputs, and drives the output with the selected output swing and de-emphasis.

Low-Power Modes

Device supports three low-power modes as described in Sleep Mode, RX Detect Mode, and U2/U3 Mode.

Sleep Mode

Initiated anytime EN_RXD undergoes a high to low transition and stays low or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode maximum current consumption is 0.1 mA. Entry time is 2 µs, the device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, and exit time is 100 µs maximum. Table 5 lists the control pin settings for sleep mode.

Table 5. Control Pin Settings

1 (default) Normal operation
0 Sleep mode

RX Detect Mode

This mode is only achievable when no remote device is connected.

Anytime SN65LVPE502x detects a break in link (that is, when upstream device is disconnected) or after power up fails to find a remote device, SN65LVPE502x goes to Rx Detect mode and conserves power by shutting down majority of its internal circuitry. In this mode, the input termination for both channels is driven to Hi-Z. In Rx Detect mode the maximum device current consumption is 5mA, which is about the 5% of its normal operating power. This feature is useful in saving system power in mobile applications, such as notebook PCs, where battery life is critical. Anytime an upstream device gets reconnected, the redriver automatically senses the connection and goes to normal operating mode. This operation requires no setting to the device.

U2/U3 Mode

With the help of internal timers, the device tracks when link enters USB 3.0 low power modes U2 and U3; in these modes, link is in electrical idle state. SN65LVPE502x selectively turns off internal circuitry to save on power. Typical power saving is about 75% lower than normal operating mode. The device automatically reverts to active mode when signal activity (LFPS) is detected.