SLLSEB3C March   2012  – November 2016 SN65LVPE502A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
      1. 6.7.1 Case I - Fixed Output, Variable Input Trace, and 3-m Cable
      2. 6.7.2 Case II - Fixed Input, Variable Output Trace, and 3-m Cable
      3. 6.7.3 Case III - Fixed Input and Variable Output Trace (No Cable)
  7. 7 Parameter Measurement Information
    1. 7.1 Typical Eye Diagram and Performance Curves
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Host- and Device-Side Pins
      2. 8.3.2 Programmable EQ, De-Emphasis and Amplitude Swing
      3. 8.3.3 Receiver Detection
        1. 8.3.3.1 At Power Up or Reset
        2. 8.3.3.2 During U2/U3 Link State
      4. 8.3.4 Electrical Idle Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Modes
        1. 8.4.2.1 Sleep Mode
        2. 8.4.2.2 RX Detect Mode
        3. 8.4.2.3 U2/U3 Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  1. The 100-nF capacitors on the TXP and SSTXN nets must be placed close to the USB connector (Type A, Type B, and so forth).
  2. The ESD and EMI protection devices (if used) must also be placed as close as possible to the USB connector.
  3. Place voltage regulators as far away as possible from the differential pairs.
  4. In general, the large bulk capacitors associated with each power rail must be placed as close as possible to the voltage regulators.
  5. TI recommends that small decoupling capacitors for the 1.8-V power rail be placed close to the SN65LVPE502x as shown below.
  6. The SuperSpeed differential pair traces for RXP/N and TXP/N must be designed with a characteristic impedance of 90 Ω ±10%. The PCB stack-up and materials determine the width and spacing required for a characteristic impedance of 90 Ω.
  7. The SuperSpeed differential pair traces must be routed parallel to each other as much as possible. TI recommends the traces be symmetrical.
  8. To minimize crosstalk, TI recommends keeping high-speed signals away from each other. Each pair must be separated by at least 5 times the signal trace width. Separating with ground also helps minimize crosstalk.
  9. Route all differential pairs on the same layer adjacent to a solid ground plane.
  10. Do not route differential pairs over any plane split.
  11. Adding test points causes impedance discontinuity and therefore negatively impacts signal performance. If test points are used, they must be placed in series and symmetrically. They must not be placed in a manner that causes stub on the differential pair.
  12. Match the etch lengths of the differential pair traces. There must be less than 5-mils difference between a SS differential pair signal and its complement. The USB 2.0 differential pairs must not exceed 50-mils relative trace length difference.
  13. The etch lengths of the differential pair groups do not need to match (that is, the length of the RXP/N pair to that of the TXP/N pair), but all trace lengths must be minimized.
  14. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure that the same via type and placement are used for both signals in a pair. Any vias used must be placed as close as possible to the SN65LVPE502x device.
  15. To ease routing, the polarity of the SS differential pairs can be swapped. This means that TXP can be routed to TXN or RXN can be routed to RXP.
  16. Do not place power fuses across the differential pair traces.

11.2 Layout Example

SN65LVPE502A SN65LVPE502B layout_example_llseb3.gif Figure 34. SN65LVPE502A USB 3.0 Signals Routing With Embedded Host and Std. Type A Connector