SLASEV8 December   2020 TAS5822M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
      2. 6.7.2 Parallel Bridge Tied Load (PBTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
    8. 6.8 Parametric Measurement Information
      1. 6.8.1 Power Consumption Summary
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Minimize EMI with Spread Spectrum
      4. 7.4.4 Minimize EMI with channel to channel phase shift
      5. 7.4.5 Minimize EMI with Multi-Devices PWM Phase Synchronization
      6. 7.4.6 Thermal Foldback
      7. 7.4.7 Device State Control
      8. 7.4.8 Device Modulation
        1. 7.4.8.1 BD Modulation
        2. 7.4.8.2 1SPW Modulation
        3. 7.4.8.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Slave Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Over current Shutdown (OCSD)
          2. 7.5.3.3.2 Speaker DC Protection
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Over Voltage Protection
          5. 7.5.3.3.5 Under Voltage Protection
          6. 7.5.3.3.6 Clock Fault
    6. 7.6 Register Maps
      1. 7.6.1 CONTROL PORT Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 2.0 (Stereo BTL) System
      2. 8.2.2 MONO （PBTL) System
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Bootstrap Capacitors
          2. 8.2.2.2.2 Inductor Selections
          3. 8.2.2.2.3 Power Supply Decoupling
          4. 8.2.2.2.4 Output EMI Filtering
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 DVDD Supply
    2. 9.2 PVDD Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines for Audio Amplifiers
      2. 10.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 10.1.3 Optimizing Thermal Performance
        1. 10.1.3.1 Device, Copper, and Component Layout
        2. 10.1.3.2 Stencil Pattern
          1. 10.1.3.2.1 PCB footprint and Via Arrangement
          2. 10.1.3.2.2 Solder Stencil
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 CONTROL PORT Registers

GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_TABLE_1 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 7-7 CONTROL PORT Registers
Offset Acronym Register Name Section
1h RESET_CTRL Register 1 Go
2h DEVICE_CTRL_1 Register 2 Go
3h DEVICE_CTRL_2 Register 3 Go
Fh I2C_PAGE_AUTO_INC Register 15 Go
28h SIG_CH_CTRL Register 40 Go
29h CLOCK_DET_CTRL Register 41 Go
30h SDOUT_SEL Register 48 Go
31h I2S_CTRL Register 49 Go
33h SAP_CTRL1 Register 51 Go
34h SAP_CTRL2 Register 52 Go
35h SAP_CTRL3 Register 53 Go
37h FS_MON Register 55 Go
38h BCK_MON Register 56 Go
39h CLKDET_STATUS Register 57 Go
4Ch DIG_VOL Register 76 Go
4Eh DIG_VOL_CTRL1 Register 78 Go
4Fh DIG_VOL_CTRL2 Register 79 Go
50h AUTO_MUTE_CTRL Register 80 Go
51h AUTO_MUTE_TIME Register 81 Go
52h AMUTE_DELAY Register 82 Go
53h ANA_CTRL Register 83 Go
54h AGAIN Register 84 Go
5Ch BQ_WR_CTRL1 Register 92 Go
5Dh DAC_CTRL Register 93 Go
60h ADR_PIN_CTRL Register 96 Go
61h ADR_PIN_CONFIG Register 97 Go
66h DSP_MISC Register 102 Go
67h DIE_ID Register 103 Go
68h POWER_STATE Register 104 Go
69h AUTOMUTE_STATE Register 105 Go
6Ah PHASE_CTRL Register 106 Go
6Bh SS_CTRL0 Register 107 Go
6Ch SS_CTRL1 Register 108 Go
6Dh SS_CTRL2 Register 109 Go
6Eh SS_CTRL3 Register 110 Go
6Fh SS_CTRL4 Register 111 Go
70h CHAN_FAULT Register 112 Go
71h GLOBAL_FAULT1 Register 113 Go
72h GLOBAL_FAULT2 Register 114 Go
73h OT WARNING Register 115 Go
74h PIN_CONTROL1 Register 116 Go
75h PIN_CONTROL2 Register 117 Go
78h FAULT_CLEAR Register 120 Go

Complex bit access types are encoded to fit into small table cells. GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_LEGEND shows the codes that are used for access types in this section.

Table 7-8 CONTROL PORT Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]

RESET_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_RESET_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_RESET_CTRL_TABLE.

Return to Summary Table.

Figure 7-17 RESET_CTRL Register
7 6 5 4 3 2 1 0
RESERVED RST_MOD RESERVED RST_REG
R/W W R W
Table 7-9 RESET_CTRL Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 000

This bit is reserved
4 RST_MOD W 0

WRITE CLEAR BIT

Reset Modules

WRITE CLEAR BIT Reset full digital core This bit resets full digital signal chain (Include DSP and Control Port Registers). Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP.

0: Normal

1: Reset modules
3-1 RESERVED R 000

This bit is reserved
0 RST_CONTROL_REG W 0

WRITE CLEAR BIT

Reset Registers

This bit resets the control port registers back to their initial values. The RAM content is not cleared.

0: Normal

1: Reset control port registers

7.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]

DEVICE_CTRL_1 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DEVICE_CTRL_1_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DEVICE_CTRL_1_TABLE.

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Figure 7-18 DEVICE_CTRL_1 Register
7 6 5 4 3 2 1 0
RESERVED FSW_SEL RESERVED DAMP_PBTL DAMP_MOD
R/W R/W R/W R/W R/W
Table 7-10 DEVICE_CTRL_1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0

This bit is reserved
6-4 FSW_SEL R/W 000 SELECT FSW. 000:768K
001:384K
010:310K
011:480K
100:576K
101:1.024MHz
110:Reserved
111:Reserved
3 RESERVED R/W 0

This bit is reserved
2 DAMP_PBTL R/W 0 0: SET DAMP TO BTL MODE
1:SET DAMP TO PBTL MODE
1-0 DAMP_MOD R/W 00

00: BD MODE

01: 1SPW MODE (Recommended)

10: HYBRID MODE (Recommended)

7.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]

DEVICE_CTRL_2 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DEVICE_CTRL_2_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DEVICE_CTRL_2_TABLE.

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Figure 7-19 DEVICE_CTRL_2 Register
7 6 5 4 3 2 1 0
RESERVED DIS_DSP MUTE RESERVED CTRL_STATE
R/W R/W R/W R/W R/W
Table 7-11 DEVICE_CTRL_2 Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 000

This bit is reserved
4 DIS_DSP R/W 1 DSP reset
When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3 MUTE R/W 0 Mute both Left Channel and Right Channel
This bit issues soft mute request for the left channel and right channel. The volume will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2 Reserved R/W 0 This bit is reserved
1-0 CTRL_STATE R/W 00 Device state control register
00: Deep Sleep
01: Sleep
10: Hiz,
11: PLAY

7.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]

I2C_PAGE_AUTO_INC is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_I2C_PAGE_AUTO_INC_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_I2C_PAGE_AUTO_INC_TABLE.

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Figure 7-20 I2C_PAGE_AUTO_INC Register
7 6 5 4 3 2 1 0
RESERVED PAGE_AUTOINC_REG RESERVED
R/W R/W R/W
Table 7-12 I2C_PAGE_AUTO_INC Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0000

This bit is reserved
3 PAGE_AUTOINC_REG R/W 0 Page auto increment disable
Disable page auto increment mode. for non -zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
2-0 RESERVED R/W 000

This bit is reserved

7.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]

SIG_CH_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SIG_CH_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SIG_CH_CTRL_TABLE.

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Figure 7-21 SIG_CH_CTRL Register
7 6 5 4 3 2 1 0
BCK_RATIO_CONFIGURE FS_MODE
R/W R/W
Table 7-13 SIG_CH_CTRL Register Field Descriptions
Bit Field Type Reset Description
7-4 BCK_RATIO_CONFIGURE R/W 0000 These bits indicate the configured BCK ratio, the number of BCK clocks in one audio frame.
4'b0011:32FS
4'b0101:64FS
4'b0111:128FS
4'b1001:256FS
4'b1011:512FS
3-0 FS_MODE R/W 0000 FS Speed Mode These bits select the FS operation mode, which must be set according to the current audio sampling rate.
4 'b0000 Auto detection
4 'b0110 32KHz
4 'b1000 44.1KHz
4'b1001 48KHz
4 'b1010 88.2KHz
4 'b1011 96KHz
Others Reserved

7.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]

CLOCK_DET_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_CLOCK_DET_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_CLOCK_DET_CTRL_TABLE.

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Figure 7-22 CLOCK_DET_CTRL Register
7 6 5 4 3 2 1 0
RESERVED DIS_DET_PLL DIS_DET_BCLK_RANGE DIS_DET_FS DIS_DET_BCLK DIS_DET_MISS RESERVED DIS_DET_LOCK
R/W R/W R/W R/W R/W R/W R/W R/W
Table 7-14 CLOCK_DET_CTRL Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0

This bit is reserved
6 DIS_DET_PLL R/W 0 Ignore PLL overate Detection
This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150MHz or an error will be reported. When ignored, a PLL overrate error will not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5 DIS_DET_BCLK_RANGE R/W 0 Ignore BCK Range Detection
This bit controls whether to ignore the BCK range detection. The BCK must be stable between 256KHz and 50MHz or an error will be reported. When ignored, a BCK range error will not cause a clock error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4 DIS_DET_FS R/W 0 Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When ignored, FS error will not cause a clock error.But CLKDET_STATUS will report fs error.
0: Regard FS detection
1: Ignore FS detection
3 DIS_DET_BCLK R/W 0 Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS and 512FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error.
0: Regard BCK detection
1: Ignore BCK detection
2 DIS_DET_MISS R/W 0 Ignore BCK Missing Detection
This bit controls whether to ignore the BCK missing detection. When ignored an BCK missing will not cause a clock error.
0: Regard BCK missing detection
1: Ignore BCK missing detection
1 RESERVED R/W 0

This bit is reserved
0 DIS_DET_LOCK R/W 0

This bit is reserved

7.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]

SDOUT_SEL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SDOUT_SEL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SDOUT_SEL_TABLE.

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Figure 7-23 SDOUT_SEL Register
7 6 5 4 3 2 1 0
RESERVED SDOUT_SEL
R/W
Table 7-15 SDOUT_SEL Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED 0

This bit is reserved
0 SDOUT_SEL R 0

SDOUT Select.

This bit selects what is being output as SDOUT pin.

0: SDOUT is the DSP output (post-processing)

1: SDOUT is the DSP input (pre-processing)

7.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]

I2S_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_I2S_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_I2S_CTRL_TABLE.

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Figure 7-24 I2S_CTRL Register
7 6 5 4 3 2 1 0
RESERVED BCK_INV RESERVED RESERVED RESERVED
R/W R/W R/W R R R/W
Table 7-16 I2S_CTRL Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 00

This bit is reserved
5 BCK_INV R/W 0 BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the BCK.
0: Normal BCK mode
1: Inverted BCK mode
4-0 RESERVED R/W 00000

This bit is reserved

7.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]

SAP_CTRL1 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL1_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL1_TABLE.

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Figure 7-25 SAP_CTRL1 Register
7 6 5 4 3 2 1 0
I2S_SHIFT_MSB DATA_FORMAT I2S_LRCLK_PULSE WORD_LENGTH
R/W R/W R/W R/W
Table 7-17 SAP_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-6 I2S_SHIFT_MSB R/W 00

I2S Shift MSB [9:8].

See details in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL2_TABLE.
5-4 DATA_FORMAT R/W 00 I2S Data Format
These bits control both input and output audio interface formats for DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2 I2S_LRCLK_PULSE R/W 00

01: lrclk pulse < 8 SCLK
1-0 WORD_LENGTH R/W 10 I2S Word Length
These bits control both input and output audio interface sample word lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits

7.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]

SAP_CTRL2 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL2_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL2_TABLE.

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Figure 7-26 SAP_CTRL2 Register
7 6 5 4 3 2 1 0
I2S_SHIFT
R/W
Table 7-18 SAP_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-0 I2S_SHIFT R/W 00000000 I2S Shift LSB [7:0]
These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio sample. I2S Shift MSB [9:8] locates in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL1.
000000000: offset = 0 BCK (no offset)
000000001: ofsset = 1 BCK
000000010: offset = 2 BCKs
and
111111111: offset = 512 BCKs

7.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]

SAP_CTRL3 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL3_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SAP_CTRL3_TABLE.

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Figure 7-27 SAP_CTRL3 Register
7 6 5 4 3 2 1 0
RESERVED LEFT_DAC_DPATH RESERVED RIGHT_DAC_DPATH
R/W R/W R/W R/W
Table 7-19 SAP_CTRL3 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 00

This bit is reserved
5-4 LEFT_DAC_DPATH R/W 01

Left DAC Data Path. These bits control the left channel audio data path connection.

00: Zero data (mute)

01: Left channel data

10: Right channel data

11: Reserved (do not set)
3-2 RESERVED R/W 00

This bit is reserved
1-0 RIGHT_DAC_DPATH R/W 01

Right DAC Data Path. These bits control the right channel audio data path connection.

00: Zero data (mute)

01: Right channel data

10: Left channel data

11: Reserved (do not set)

7.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]

FS_MON is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FS_MON_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FS_MON_TABLE.

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Figure 7-28 FS_MON Register
7 6 5 4 3 2 1 0
RESERVED BCLK_RATIO_HIGH FS
R/W R R
Table 7-20 FS_MON Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 00

This bit is reserved
5-4 BCLK_RATIO_HIGH R 00

2 msbs of detected BCK ratio
3-0 FS R 0000 These bits indicate the currently detected audio sampling rate.
0000 FS Error
0010 8KHz
0100 16KHz
0110 32KHz
1000 Reserved
1001 48KHz
1011 96KHz
1101 192KHz
Others Reserved

7.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]

BCK_MON is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_BCK_MON_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_BCK_MON_TABLE.

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Figure 7-29 BCK_MON Register
7 6 5 4 3 2 1 0
BCLK_RATIO_LOW
R
Table 7-21 BCK_MON Register Field Descriptions
Bit Field Type Reset Description
7-0 BCLK_RATIO_LOW R 00000000

These bits indicate the currently detected BCK ratio, the number of BCK clocks in one audio frame.

BCK = 32 FS~512 FS

7.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]

CLKDET_STATUS is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_CLKDET_STATUS_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_CLKDET_STATUS_TABLE.

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Figure 7-30 CLKDET_STATUS Register
7 6 5 4 3 2 1 0
RESERVED DET_STATUS
R/W R
Table 7-22 CLKDET_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 00

This bit is reserved
5 DET_STATUS R 0 This bit indicates whether the BCLK is overrate or underrate
4 R 0 This bit indicates whether the PLL is overrate
3 R 0 This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.
2 R 0 This bit indicates whether the BCK is missing or not.
1 R 0 This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-512FS to be valid.
0 R 0 In auto detection mode(reg_fsmode=0),this bit indicated whether the audio sampling rate is valid or not. In non auto detection mode(reg_fsmode!=0), Fs error indicates that configured fs is different with detected fs. Even FS Error Detection Ignore is set, this flag will be also asserted.

7.6.1.15 DIG_VOL Register (Offset = 4Ch) [reset = 30h]

DIG_VOL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIG_VOL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIG_VOL_TABLE.

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Figure 7-31 DIG_VOL Register
7 6 5 4 3 2 1 0
PGA_LEFT
R/W
Table 7-23 DIG_VOL Register Field Descriptions
Bit Field Type Reset Description
7-0 PGA R/W 00110000 Digital Volume
These bits control both left and right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute

7.6.1.16 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL1 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIG_VOL_CTRL1_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIG_VOL_CTRL1_TABLE.

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Figure 7-32 DIG_VOL_CTRL1 Register
7 6 5 4 3 2 1 0
PGA_RAMP_DOWN_SPEED PGA_RAMP_DOWN_STEP PGA_RAMP_UP_SPEED PGA_RAMP_UP_STEP
R/W R/W R/W R/W
Table 7-24 DIG_VOL_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-6 PGA_RAMP_DOWN_SPEED R/W 00 Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4 PGA_RAMP_DOWN_STEP R/W 11 Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-2 PGA_RAMP_UP_SPEED R/W 00 Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
1-0 PGA_RAMP_UP_STEP R/W 11 Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the volume is ramping up.
00: Increment by 4 dB for each updat
e 01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update

7.6.1.17 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]

DIG_VOL_CTRL2 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIG_VOL_CTRL2_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIG_VOL_CTRL2_TABLE.

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Figure 7-33 DIG_VOL_CTRL2 Register
7 6 5 4 3 2 1 0
FAST_RAMP_DOWN_SPEED FAST_RAMP_DOWN_STEP RESERVED
R/W R/W R/W
Table 7-25 DIG_VOL_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-6 FAST_RAMP_DOWN_SPEED R/W 00 Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4 FAST_RAMP_DOWN_STEP R/W 11 Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0 RESERVED R/W 0000

This bit is reserved

7.6.1.18 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]

AUTO_MUTE_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AUTO_MUTE_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AUTO_MUTE_CTRL_TABLE.

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Figure 7-34 AUTO_MUTE_CTRL Register
7 6 5 4 3 2 1 0
RESERVED REG_AUTO_MUTE_CTRL
R/W R/W
Table 7-26 AUTO_MUTE_CTRL Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R/W 00000

This bit is reserved
2 REG_AUTO_MUTE_CTRL R/W 1 0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are about to be auto muted.
1 1 0: Disable right channel auto mute
1: Enable right channel auto mute
0 1 0: Disable left channel auto mute
1: Enable left channel auto mute

7.6.1.19 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]

AUTO_MUTE_TIME is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AUTO_MUTE_TIME_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AUTO_MUTE_TIME_TABLE.

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Figure 7-35 AUTO_MUTE_TIME Register
7 6 5 4 3 2 1 0
RESERVED AUTOMUTE_TIME_LEFT RESERVED AUTOMUTE_TIME_RIGHT
R/W R/W R/W R/W
Table 7-27 AUTO_MUTE_TIME Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0

This bit is reserved
6-4 AUTOMUTE_TIME_LEFT R/W 000 Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3 RESERVED R/W 0

This bit is reserved
2-0 AUTOMUTE_TIME_RIGHT R/W 000 Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec

7.6.1.20 AMUTE_DELAY Register (Offset = 52h) [reset = 0x00]

AMUTE_DELAY is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AMUTE_DELAY_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AMUTE_DELAY_TABLE.

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Figure 7-36 AMUTE_DELAY Register
7 6 5 4 3 2 1 0
AMUTE_DLY
R/W
Table 7-28 AMUTE_DELAY Register Field Descriptions
Bit Field Type Reset Description
7-0 AMUTE_DLY R/W 00000000 AMUTE Delay
These bits control the delay before the complete digital mute to the assertion of analog mute. This is to allow the non-mute audio samples to completely flow out through analog parts before the assertion of the analog mute.
00000000: No delay
00000001: 1 LRCK delay
00000010: 2 LRCK delay
......
11111111: 255 LRCK delay

7.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0x00]

ANA_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_ANA_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_ANA_CTRL_TABLE.

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Figure 7-37 ANA_CTRL Register
7 6 5 4 3 2 1 0
ANA_CTRL
R/W
Table 7-29 ANA_CTRL Register Field Descriptions
Bit Field Type Reset Description
7 ANA_CTRL R/W 0

Fast Hiz control enable in clock halt
6-5 00

Class-D bandwidth control, "00": 80kHz; "01": 100kHz; "10": 120kHz; "11": 175kHz.

With 768kHz or 1.024MHz switching frequency, bandwidth need set to 175kHz for best audio performance
4-1 0000

These bits are reserved
0 0

Channel L and R PWM output of phase control .

1: In phase

0: Out of phase

7.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]

AGAIN is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AGAIN_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AGAIN_TABLE.

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Figure 7-38 AGAIN Register
7 6 5 4 3 2 1 0
RESERVED ANA_GAIN
R/W R/W
Table 7-30 AGAIN Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 000

This bit is reserved
4-0 ANA_GAIN R/W 00000 Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001:-0.5db
11111: -15.5 dB

7.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]

BQ_WR_CTRL1 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_BQ_WR_CTRL1_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_BQ_WR_CTRL1_TABLE.

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Figure 7-39 BQ_WR_CTRL1 Register
7 6 5 4 3 2 1 0
RESERVED BQ_WR_FIRST_COEF
R/W R/W
Table 7-31 BQ_WR_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R/W 0000000

This bit is reserved
0 BQ_WR_FIRST_COEF R/W 0

Indicate the first coefficient of a BQ is starting to write.

7.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]

DAC_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DAC_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DAC_CTRL_TABLE.

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Figure 7-40 DAC_CTRL Register
7 6 5 4 3 2 1 0
DAC_FREQUENCY_SEL DAC_DITHER_EN DAC_DITHER DAC_CTRL_DEM_SEL
R/W R/W R/W R/W
Table 7-32 DAC_CTRL Register Field Descriptions
Bit Field Type Reset Description
7 DAC_FREQUENCY_SEL R/W 1

DAC Frequency Selection

0: 6.144MHz

1: 3.072MHz
6-5 DAC_DITHER_EN R/W 11 DITHER_EN,
00: Disable both stage dither
01: Enable main stage dither
10: Enable second stage dither
11: Enable both stage dither
4-2 DAC_DITHER R/W 110 Dither level
100: -2^-7
101: -2^-8
110: -2^-9
111: -2^-10
000: -2^-13
001: -2^-14
010: -2^-15
011: -2^-16
1-0 DAC_CTRL_DEM_SEL R/W 00

00: Enable DAC DEM (Dynamic-Element-Matching)

11: Disable DAC DEM (Dynamic-Element-Matching)

7.6.1.25 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]

ADR_PIN_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_ADR_PIN_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_ADR_PIN_CTRL_TABLE.

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Figure 7-41 ADR_PIN_CTRL Register
7 6 5 4 3 2 1 0
RESERVED ADR_OE
R/W - 0x0
Table 7-33 ADR_PIN_CTRL Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R/W 0000000

This bit is reserved
0 ADR_OE R/W 0

ADR Output Enable

This bit sets the direction of the ADR pin

0: ADR is input

1: ADR is output

7.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]

ADR_PIN_CONFIG is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_ADR_PIN_CONFIG_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_ADR_PIN_CONFIG_TABLE.

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Figure 7-42 ADR_PIN_CONFIG Register
7 6 5 4 3 2 1 0
RESERVED ADR_PIN_CONFIG
R/W
Table 7-34 ADR_PIN_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 000

This bit is reserved
4-0 ADR_PIN_CONFIG R/W 00000

00000: off (low)

00011: Auto mute flag (asserted when both L and R channels are auto muted)

00100: Auto mute flag for left channel

00101: Auto mute flag for right channel

00110: Clock invalid flag (clock error or clock missing)

00111: Reserved

01000: Reserved

01001: Reserved

01011: ADR as FAULTZ output

7.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]

DSP_MISC is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DSP_MISC_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DSP_MISC_TABLE.

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Figure 7-43 DSP_MISC Register
7 6 5 4 3 2 1 0
BYPASS_CONTROL
R/W
Table 7-35 DSP_MISC Register Field Descriptions
Bit Field Type Reset Description
7-4 BYPASS CONTROL R/W 0000

These bits are reserved
3 0

1: Left and Right will have use unique coef

0: Right channel will share left channel coefficient
2 0

This bit is reserved
1 0

1: Bypass DRC
0 0

1: Bypass EQ

7.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]

DIE_ID is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIE_ID_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_DIE_ID_TABLE.

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Figure 7-44 DIE_ID Register
7 6 5 4 3 2 1 0
DIE_ID
R-0h
Table 7-36 DIE_ID Register Field Descriptions
Bit Field Type Reset Description
7-0 DIE_ID R 0h

DIE ID

7.6.1.29 POWER_STATE Register (Offset = 68h) [reset = 0x00]

POWER_STATE is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_POWER_STATE_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_POWER_STATE_TABLE.

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Figure 7-45 POWER_STATE Register
7 6 5 4 3 2 1 0
STATE_RPT
R
Table 7-37 POWER_STATE Register Field Descriptions
Bit Field Type Reset Description
7-2 Reserved R 000000

These bits are reserved
1-0 STATE_RPT R 00

00: Deep sleep

01: Seep

10: HIZ

11: Play

7.6.1.30 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]

AUTOMUTE_STATE is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AUTOMUTE_STATE_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_AUTOMUTE_STATE_TABLE.

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Figure 7-46 AUTOMUTE_STATE Register
7 6 5 4 3 2 1 0
RESERVED ZERO_RIGHT_MON ZERO_LEFT_MON
R R R
Table 7-38 AUTOMUTE_STATE Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 000000

This bit is reserved
1 ZERO_RIGHT_MON R 0

This bit indicates the auto mute status for right channel.

0: Not auto muted

1: Auto muted
0 ZERO_LEFT_MON R 0

This bit indicates the auto mute status for left channel.

0: Not auto muted

1: Auto muted

7.6.1.31 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]

PHASE_CTRL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_PHASE_CTRL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_PHASE_CTRL_TABLE.

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Figure 7-47 PHASE_CTRL Register
7 6 5 4 3 2 1 0
RESERVED RAMP_PHASE_SEL I2S_SYNC_EN PHASE_SYNC _EN
R/W R/W R/W R/W
Table 7-39 PHASE_CTRL Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0000

This bit is reserved
3-2 RAMP_PHASE_SEL R/W 00

Select ramp clock phase when multi devices integrated in one system to reduce EMI and peak supply peak current, it is recomended set all devices the same RAMP frequency and same spread spectrum. it must be set before driving device into PLAY mode if this feature is needed.

00: phase 0

01: phase1

10: phase2

11: phase3
1 I2S_SYNC_EN R/W 0

Use I2S to synchronize output PWM phase

0: Disable

1: Enable
0 PHASE_SYNC_EN R/W 0

0: RAMP phase sync disable

1: RAMP phase sync enable

7.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]

SS_CTRL0 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL0_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL0_TABLE.

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Figure 7-48 SS_CTRL0 Register
7 6 5 4 3 2 1 0
RESERVED RESERVED SS_PRE_DIV_SEL SS_MANUAL_MODE RESERVED SS_RDM_EN SS_TRI_EN
R/W R/W R/W R/W R/W R/W R/W
Table 7-40 SS_CTRL0 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0

This bit is reserved
6 RESERVED R/W 0

This bit is reserved
5 SS_PRE_DIV_SEL R/W 0

Select pll clock divide 2 as source clock in manual mode
4 SS_MANUAL_MODE R/W 0

Set ramp ss controller to manual mode
3-2 RESERVED R/W 0

This bit is reserved
1 SS_RDM_EN R/W 0

Random SS enable
0 SS_TRI_EN R/W 0

Triangle SS enable

7.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]

SS_CTRL1 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL1_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL1_TABLE.

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Figure 7-49 SS_CTRL1 Register
7 6 5 4 3 2 1 0
RESERVED SS_RDM_CTRL SS_TRI_CTRL
R/W R/W R/W
Table 7-41 SS_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0

This bit is reserved
6-4 SS_RDM_CTRL R/W 000

Random SS range control
3-0 SS_TRI_CTRL R/W 0000

Triangle SS frequency and range control

7.6.1.34 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]

SS_CTRL2 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL2_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL2_TABLE.

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Figure 7-50 SS_CTRL2 Register
7 6 5 4 3 2 1 0
TM_FREQ_CTRL
R/W
Table 7-42 SS_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-0 TM_FREQ_CTRL R/W 01010000

Control ramp frequency in manual mode, F=61440000/N

7.6.1.35 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]

SS_CTRL3 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL3_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL3_TABLE.

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Figure 7-51 SS_CTRL3 Register
7 6 5 4 3 2 1 0
TM_DSTEP_CTRL TM_USTEP_CTRL
R/W R/W
Table 7-43 SS_CTRL3 Register Field Descriptions
Bit Field Type Reset Description
7-4 SS_TM_DSTEP_CTRL R/W 0001

Control triangel mode spread spectrum fall step in ramp ss manual mode
3-0 SS_TM_USTEP_CTRL R/W 0001

Control triangle mode spread spectrum rise step in ramp ss manual mode

7.6.1.36 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]

SS_CTRL4 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL4_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_SS_CTRL4_TABLE.

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Figure 7-52 SS_CTRL4 Register
7 6 5 4 3 2 1 0
RESERVED TM_AMP_CTRL SS_TM_PERIOD_BOUNDRY
R/W R/W R/W
Table 7-44 SS_CTRL4 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0

This bit is reserved
6-5 TM_AMP_CTRL R/W 01

Control ramp amp ctrl in ramp ss manual model
4-0 SS_TM_PERIOD_BOUNDRY R/W 00100

Control triangle mode spread spectrum boundary in ramp ss manual mode

7.6.1.37 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CHAN_FAULT is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_CHAN_FAULT_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_CHAN_FAULT_TABLE.

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Figure 7-53 CHAN_FAULT Register
7 6 5 4 3 2 1 0
RESERVED CH1_DC_1 CH2_DC_1 CH1_OC_I CH2_OC_I
R R R R R
Table 7-45 CHAN_FAULT Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000

This bit is reserved
3 CH1_DC_1 R 0

Left channel DC fault.

Once there is a DC fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10).

Clear this fault by setting bit 7 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR to 1 or this bit keeps 1.
2 CH2_DC_1 R 0

Right channel DC fault.

Once there is a DC fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10).

Clear this fault by setting bit 7 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR to 1 or this bit keeps 1.
1 CH1_OC_I R 0

Left channel over current fault.

Once there is an OC fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10).

Clear this fault by setting bit 7 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR to 1 or this bit keeps 1.
0 CH2_OC_I R 0

Right channel over current fault.

Once there is an OC fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10).

Clear this fault by setting bit 7 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR to 1 or this bit keeps 1.

7.6.1.38 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

GLOBAL_FAULT1 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_GLOBAL_FAULT1_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_GLOBAL_FAULT1_TABLE.

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Figure 7-54 GLOBAL_FAULT1 Register
7 6 5 4 3 2 1 0
OTP_CRC_ERROR BQ_WR_ERROR CLK_FAULT_I PVDD_OV_I PVDD_UV_I
R R R R R
Table 7-46 GLOBAL_FAULT1 Register Field Descriptions
Bit Field Type Reset Description
7 OTP_CRC_ERROR R 0h

Indicate OTP CRC check error.
6 BQ_WR_ERROR R 0h

The recent BQ is written failed
5-3 RESERVED R 0h

This bit is reserved
2 CLK_FAULT_I R 0h

Clock fault.

Once there is a Clock fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10).

Clock fault works with an auto-recovery mode, once the clock error removes, device automatically returns to the previous state.

Clear this fault by setting bit 7 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR to 1 or this bit keeps 1.
1 PVDD_OV_I R 0h

PVDD OV fault.

Once there is an OV fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state.

Clear this fault by setting bit 7 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR to 1 or this bit keeps 1.

Once OV fault been cleared by Register 0x78, even the OV fault still exist (Device still keeps in Hi-Z state due to High PVDD), PVDD_OV_I keeps 0 unless the OV fault been triggered again (PVDD drop below the OV

threshold and rise again).
0 PVDD_UV_I R 0h

PVDD UV fault.

Once there is an UV fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10).

UV fault works with an auto-recovery mode, once the UV error removes, device automatically returns to the previous state.

Clear this fault by setting bit 7 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR to 1 or this bit keeps 1.

Once UV fault been cleared by Register 0x78, even the UV fault still exist (Device still keep in Hi-Z state due to Low PVDD), PVDD_UV_I keeps 0 unless the UV fault been triggered again (PVDD rise above the UV threshold and fall again).

7.6.1.39 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

GLOBAL_FAULT2 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_GLOBAL_FAULT2_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_GLOBAL_FAULT2_TABLE.

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Figure 7-55 GLOBAL_FAULT2 Register
7 6 5 4 3 2 1 0
RESERVED RESERVED OTSD_I
R R R
Table 7-47 GLOBAL_FAULT2 Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 0000000

This bit is reserved
0 OTSD_I R 0

Over temperature shut down fault.

Once there is an OT fault, this bit will set to 1. Class D output will set to Hi-Z. Report by FAULT pin (Pin 10).

OT fault works with an auto-recovery mode by setting bit 4 of GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_MISC_CONTROL to 1, once the OT error removes, device automatically returns to the previous state.

Once OT fault been cleared by Register 0x78, even the OT still exist (Junction temperature exceed 160°C), device will start playing. This is a risk may destroy device, so suggest to set device to OT autorecovery mode or keep Hi-Z state until the OT warning disappear.

OTSD_I keeps 0 unless the OT fault been triggered again

(Temperature drop below the threshold and exceed the threshold again).

7.6.1.40 OT WARNING Register (Offset = 73h) [reset = 0x00]

OT_WARNING is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_OT_WARNING_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_OT_WARNING_TABLE.

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Figure 7-56 OT_WARNING Register
7 6 5 4 3 2 1 0
RESERVED RESERVED OTW RESERVED
R R R R R R
Table 7-48 OT_WARNING Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00

This bit is reserved
5-4 RESERVED R 00

This bit is reserved
3 OTW R 0

Over temperature warning ,135C
2-0 RESERVED R 000

This bit is reserved

7.6.1.41 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]

PIN_CONTROL1 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_PIN_CONTROL1_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_PIN_CONTROL1_TABLE.

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Figure 7-57 PIN_CONTROL1 Register
7 6 5 4 3 2 1 0
MASK_OTSD Reserved Reserved MASK_CLK_FAULT MASK_PVDD_UV MASK_PVDD_OV MASK_DC MASK_OC
R/W R/W R/W R/W R/W R/W R/W R/W
Table 7-49 PIN_CONTROL1 Register Field Descriptions
Bit Field Type Reset Description
7 MASK_OTSD R/W 0

Mask OTSD fault report
6 RESERVED R/W 0 This bit is reserved
5 RESERVED R/W 0

This bit is reserved
4 MASK_CLK_FAULT R/W 0

Mask clock fault report by setting this bit to 1.
3 MASK_PVDD_UV R/W 0

Mask PVDD UV fault report by setting this bit to 1.
2 MASK_PVDD_OV R/W 0

Mask PVDD OV fault report by setting this bit to 1.
1 MASK_DC R/W 0

Mask DC fault report by setting this bit to 1.
0 MASK_OC R/W 0

Mask OC fault report by setting this bit to 1.

7.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]

PIN_CONTROL2 is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_PIN_CONTROL2_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_PIN_CONTROL2_TABLE.

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Figure 7-58 PIN_CONTROL2 Register
7 6 5 4 3 2 1 0
RESERVED CLKFLT_LATCH_EN OTSD_LATCH_EN OTW_LATCH_EN MASK_OTW RESERVED
R/W R/W R/W R/W
Table 7-50 PIN_CONTROL2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 11

This bit is reserved
5 CLKFLT_LATCH_EN R/W 1

Enable clock fault latch by setting this bit to 1.
4 OTSD_LATCH_EN R/W 1

Enable OTSD fault latch by setting this bit to 1.
3 OTW_LATCH_EN R/W 1

Enable OT warning latch by setting this bit to 1.
2 MASK_OTW R/W 0

Mask OT warning report by setting this bit to 1.
1-0 RESERVED R/W 00

This bit is reserved

7.6.1.43 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]

MISC_CONTROL is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_MISC_CONTROL_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_MISC_CONTROL_TABLE.

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Figure 7-59 MISC_CONTROL Register
7 6 5 4 3 2 1 0
DET_STATUS_LATCH RESERVED OTSD_AUTO_REC_EN RESERVED
R/W R/W R/W R/W
Table 7-51 MISC_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7 DET_STATUS_LATCH R/W 0

1:Latch clock detection status

0:Don't latch clock detection status
6-5 RESERVED R/W 00

This bit is reserved
4 OTSD_AUTO_REC_EN R/W 0

OTSD auto recovery enable by setting this bit to 1.
3-0 RESERVED R/W 0000

This bit is reserved

7.6.1.44 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]

FAULT_CLEAR is shown in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR_FIGURE and described in GUID-04C5FEC8-D23E-4DF1-8CC1-124BCE165B89.html#CONTROL_PORT_FAULT_CLEAR_TABLE.

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Figure 7-60 FAULT_CLEAR Register
7 6 5 4 3 2 1 0
ANALOG_FAULT_CLEAR RESERVED
W R/W
Table 7-52 FAULT_CLEAR Register Field Descriptions
Bit Field Type Reset Description
7 ANALOG_FAULT_CLEAR W 0

WRITE CLEAR BIT once write this bit to 1, device will clear analog fault
6-0 RESERVED R/W 0000000

This bit is reserved