SLASEV8 December   2020 TAS5822M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
      2. 6.7.2 Parallel Bridge Tied Load (PBTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
    8. 6.8 Parametric Measurement Information
      1. 6.8.1 Power Consumption Summary
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Minimize EMI with Spread Spectrum
      4. 7.4.4 Minimize EMI with channel to channel phase shift
      5. 7.4.5 Minimize EMI with Multi-Devices PWM Phase Synchronization
      6. 7.4.6 Thermal Foldback
      7. 7.4.7 Device State Control
      8. 7.4.8 Device Modulation
        1. 7.4.8.1 BD Modulation
        2. 7.4.8.2 1SPW Modulation
        3. 7.4.8.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Slave Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Over current Shutdown (OCSD)
          2. 7.5.3.3.2 Speaker DC Protection
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Over Voltage Protection
          5. 7.5.3.3.5 Under Voltage Protection
          6. 7.5.3.3.6 Clock Fault
    6. 7.6 Register Maps
      1. 7.6.1 CONTROL PORT Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 2.0 (Stereo BTL) System
      2. 8.2.2 MONO （PBTL) System
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Bootstrap Capacitors
          2. 8.2.2.2.2 Inductor Selections
          3. 8.2.2.2.3 Power Supply Decoupling
          4. 8.2.2.2.4 Output EMI Filtering
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 DVDD Supply
    2. 9.2 PVDD Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines for Audio Amplifiers
      2. 10.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 10.1.3 Optimizing Thermal Performance
        1. 10.1.3.1 Device, Copper, and Component Layout
        2. 10.1.3.2 Stencil Pattern
          1. 10.1.3.2.1 PCB footprint and Via Arrangement
          2. 10.1.3.2.2 Solder Stencil
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Serial Audio Port - Data Formats and Bit Depths

The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and TDM/DSP data. Data formats are selected via Register (Register Address 0x33-D[5:4]). If the high width of LRCLK(FS) in TDM/DSP mode is less than 8 cycles of SCLK(BCLK), the register (Register Address 0x33-D[3:2]) should set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word length and clock rate supported by this device are shown in Table 1. The data formats are detailed in Figure 1 through Figure 6. The word length are selected via Register (Register Address 0x33-D[1:0]).Default setting is I2S and 24 bit word length.

For TDM Mode, the offsets of data are selected via Register (Register Address 0x33-D[7-6]) and Register (Register Address 0x34-D[7:0]).

Table 7-2 TDM Slots vs FS
LRCLK(FS)TDM SlotsNotes
48kHz16Each Slots's position (offset) can be set by Register 51 (Register address 0x33) and Register 52 (Register address 0x34).
96kHz8
GUID-9D20BCFD-C910-4139-B621-9EBD79F5D34C-low.gifFigure 7-2 Left Justified Audio Data Format
GUID-58438871-F382-4FB5-80F2-706867B0559F-low.gif
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 7-3 I2S Audio Data Format
GUID-C3B6F810-F807-42F2-AEC5-49ABABE3B4D5-low.gif
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 7-4 Right Justified Audio Data Format
GUID-18853F6A-AB10-4210-A91B-25513B172A8F-low.gif
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 7-5 TDM 1 Audio Data Format
GUID-CFA37C65-C5BD-48B2-B327-625D9F0DF807-low.gif
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCLK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 7-6 TDM 2 Audio Data Format