SLOS948 February 2019 TAS6424M-Q1
All communications to the TAS6424M-Q1 are through the I2C protocol. A system controller can communicate with the device through the SDA pins and SCL pins. The TAS6424M-Q1 is an I2C slave device and requires a master. The device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by the device is 400 kHz. If multiple TAS6424M-Q1 devices are on the same I2C bus, the I2C address must be different for each device. Up to four TAS6424M-Q1 devices can be on the same I2C bus.
The I2C bus is shared internally.
Complete any internal operations, such as load diagnostics, before reading the registers for the results.