SLOS948 February 2019 TAS6424M-Q1
As shown in Figure 45, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed by a read occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be read. As a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1, indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.