SBOS780C March   2016  – June 2021 THS3215

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: D2S
    6. 6.6  Electrical Characteristics: OPS
    7. 6.7  Electrical Characteristics: D2S + OPS
    8. 6.8  Electrical Characteristics: Midscale (DC) Reference Buffer
    9. 6.9  Typical Characteristics: D2S + OPS
    10. 6.10 Typical Characteristics: D2S Only
    11. 6.11 Typical Characteristics: OPS Only
    12. 6.12 Typical Characteristics: Midscale (DC) Reference Buffer
    13. 6.13 Typical Characteristics: Switching Performance
    14. 6.14 Typical Characteristics: Gain Drift
  7. Parameter Measurement Information
    1. 7.1 Overview
    2. 7.2 Frequency Response Measurement
    3. 7.3 Harmonic Distortion Measurement
    4. 7.4 Noise Measurement
    5. 7.5 Output Impedance Measurement
    6. 7.6 Step-Response Measurement
    7. 7.7 Feedthrough Measurement
    8. 7.8 Midscale Buffer ROUT Versus CLOAD Measurement
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2 V/V (Pins 2, 3, 6, and 14)
      2. 8.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
      3. 8.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
        1. 8.3.3.1 Output DC Offset and Drift for the OPS
        2. 8.3.3.2 OPS Harmonic Distortion (HD) Performance
        3. 8.3.3.3 Switch Feedthrough to the OPS
        4. 8.3.3.4 Driving Capacitive Loads
      4. 8.3.4 Digital Control Lines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Full-Signal Path Mode
        1. 8.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
        2. 8.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
        3. 8.4.1.3 External Connection
      2. 8.4.2 Dual-Output Mode
      3. 8.4.3 Differential I/O Voltage Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Applications
        1. 9.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
          1. 9.1.1.1.1 Design Requirements
          2. 9.1.1.1.2 Detailed Design Procedure
          3. 9.1.1.1.3 Application Curves
        2. 9.1.1.2 High-Voltage Pulse-Generator
          1. 9.1.1.2.1 Design Requirements
          2. 9.1.1.2.2 Detailed Design Procedure
          3. 9.1.1.2.3 Application Curves
        3. 9.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
          1. 9.1.1.3.1 Detailed Design Procedure
        4. 9.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
          1. 9.1.1.4.1 Detailed Design Procedure
        5. 9.1.1.5 Differential I/O Driver With independent Common-Mode Control
          1. 9.1.1.5.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI (Free Software Download)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

OPS Harmonic Distortion (HD) Performance

The OPS in the THS3215 provides one of the best HD solutions available through high power levels and frequencies. Figure 6-31 and Figure 6-32 show the swept-frequency HD2 and HD3, where the second harmonic is clearly the dominant term over the third harmonic. Typical wideband CFA distortion is reported only through 2 VPP output, while Figure 6-31 and Figure 6-32 provide sweeps at 5 VPP and 8 VPP into a 100 Ω load. These curves show an approximate 20 dB per decade rise with frequency due to loop-gain roll-off.

The distortion performance is extremely robust as a function of load resistance (see Figure 6-33 and Figure 6-34). Normally, heavier loads degrade the distortion performance, as shown by the HD2 in Figure 6-33. However at frequencies greater than 30 MHz, the HD2 actually improves slightly as the output load is increased from 500 Ω to 100 Ω.

One of the key advantages offered by the CFA design in the OPS is that the distortion performance holds approximately constant over gain, as seen in the full-path distortion measurements of Figure 6-9 and Figure 6-10. Here, the D2S provides a fixed gain of 2 V/V driving a 200 Ω interstage load and using the internal path to drive the OPS at gains from 1.5 V/V to 10 V/V. Hold the loop-gain approximately constant by adjusting the feedback RF value with gain to achieve vastly improved performance versus a voltage-feedback-based design.

Testing a 5 VPP output from the OPS with the supplies swept from the minimum ±4 V to ±7.5 V in Figure 6-35 and Figure 6-36 show:

  1. The 1.5 V headroom on ±4 V supplies and ±2.5 V output voltage results in degraded performance. At the lower supplies, target lower output swings for improved linearity performance.
  2. The HD2 does not change significantly with supply voltages above ±6 V. The HD3 does improve slightly at higher supply-voltage settings.

From these plots at ±7.5 V supplies, a 5 VPP output into 100 Ω load shows better than –60 dBc HD2 and HD3 performance through 30 MHz. This exceptional performance is available with the OPS configured as a standalone amplifier. Combining the standalone OPS performance with the D2S (see Figure 6-3 and Figure 6-4) does not degrade the full, signal-path distortion levels. With the D2S and OPS running together at a final 5 VPP output and 30 MHz, the HD2 changes to –63 dBc and HD3 changes to –59 dBc on ±6 V supplies. Lower output swings for the combined stages provide much lower distortion. The 2 VPP output curves on Figure 6-3 and Figure 6-4 show –61 dBc for HD2 and HD3 at 50 MHz.