SBOS780C March   2016  – June 2021 THS3215

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: D2S
    6. 6.6  Electrical Characteristics: OPS
    7. 6.7  Electrical Characteristics: D2S + OPS
    8. 6.8  Electrical Characteristics: Midscale (DC) Reference Buffer
    9. 6.9  Typical Characteristics: D2S + OPS
    10. 6.10 Typical Characteristics: D2S Only
    11. 6.11 Typical Characteristics: OPS Only
    12. 6.12 Typical Characteristics: Midscale (DC) Reference Buffer
    13. 6.13 Typical Characteristics: Switching Performance
    14. 6.14 Typical Characteristics: Gain Drift
  7. Parameter Measurement Information
    1. 7.1 Overview
    2. 7.2 Frequency Response Measurement
    3. 7.3 Harmonic Distortion Measurement
    4. 7.4 Noise Measurement
    5. 7.5 Output Impedance Measurement
    6. 7.6 Step-Response Measurement
    7. 7.7 Feedthrough Measurement
    8. 7.8 Midscale Buffer ROUT Versus CLOAD Measurement
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2 V/V (Pins 2, 3, 6, and 14)
      2. 8.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
      3. 8.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
        1. 8.3.3.1 Output DC Offset and Drift for the OPS
        2. 8.3.3.2 OPS Harmonic Distortion (HD) Performance
        3. 8.3.3.3 Switch Feedthrough to the OPS
        4. 8.3.3.4 Driving Capacitive Loads
      4. 8.3.4 Digital Control Lines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Full-Signal Path Mode
        1. 8.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
        2. 8.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
        3. 8.4.1.3 External Connection
      2. 8.4.2 Dual-Output Mode
      3. 8.4.3 Differential I/O Voltage Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Applications
        1. 9.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
          1. 9.1.1.1.1 Design Requirements
          2. 9.1.1.1.2 Detailed Design Procedure
          3. 9.1.1.1.3 Application Curves
        2. 9.1.1.2 High-Voltage Pulse-Generator
          1. 9.1.1.2.1 Design Requirements
          2. 9.1.1.2.2 Detailed Design Procedure
          3. 9.1.1.2.3 Application Curves
        3. 9.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
          1. 9.1.1.3.1 Detailed Design Procedure
        4. 9.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
          1. 9.1.1.4.1 Detailed Design Procedure
        5. 9.1.1.5 Differential I/O Driver With independent Common-Mode Control
          1. 9.1.1.5.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI (Free Software Download)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics: D2S

at +VCC = 6.0 V, –VCC = –6.0 V, AV = 2 V/V, 25-Ω source impedance, input common-mode voltage (VIC) = 0.25 V, external OPS input selected (PATHSEL ≥ 1.3 V), VREF = GND, RLOAD = 100 Ω, and TJ ≈ 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST LEVEL (1)
AC PERFORMANCE (Power Stage Disabled: DISABLE pin ≥ 1.3 V) (5)
Small-signal bandwidth (SSBW)VOUT = 250 mVPP, peaking < 1.0 dB450MHzC
Large-signal bandwidth (LSBW)VOUT = 2 VPP350MHzC
Bandwidth for 0.2-dB flatnessVOUT = 2 VPP65MHzC
Slew rate(2)VOUT = 4-V step1500V/µsC
Overshoot and undershootInput tr = 1 ns, VOUT = 2-V step2%C
Rise and fall timeInput tr = 1 ns, VOUT = 2-V step1.2nsC
Settling time to 0.1%Input tr = 1 ns, VOUT = 2-V step5nsC
2nd-order harmonic distortion (HD2)f = 20 MHz, VOUT = 2 VPP–72dBcC
3rd-order harmonic distortion (HD3)f = 20 MHz, VOUT = 2 VPP–88dBcC
Output voltage noisef > 200 kHz12nV/√ HzC
Input current noise (each input)f > 200 kHz2.0pA/√ HzC
Output impedancef = 20 MHz0.9ΩC
DC PERFORMANCE (5)
Differential to single-ended gain±100-mV output1.9752.02.025V/VA
Differential to single-ended gain driftTJ = –40°C to +125°C3743ppm/°CB
VREF input pin gainDifferential inputs = 0 V,
VREF = ±100 mV
0.9751.01.015V/VA
VREF input pin gain driftTJ = –40°C to +125°C–67–74ppm/°CB
Output offset voltageTJ ≈ 25°C–35±835mVA
TJ = 0°C to 70°C–3736mVB
TJ = –40°C to +125°C–3938mVB
Output offset voltage driftTJ = –40°C to +125°C–4–25–45µV/°CB
Input bias current – each input(3)TJ ≈ 25°C–4±24µAA
TJ = 0°C to 70°C–4.24.3µAB
TJ = –40°C to +125°C–4.34.5µAB
Input bias current driftTJ = –40°C to +125°C345nA/°CB
Input offset currentTJ ≈ 25°C–400±50400nAA
TJ = 0°C to 70°C–475535nAB
TJ = –40°C to +125°C–595700nAB
Input offset current driftTJ = –40°C to +125°C–30.23nA/°CB
INPUTS(4)
Common-mode input negative supply headroomTJ ≈ 25°C1.81.9VA
TJ = –40°C to +85°C2.0VB
Common-mode input positive supply headroomTJ ≈ 25°C1.31.4VA
TJ = –40°C to +125°C1.5VB
Common-mode rejection ratio (CMRR)–1 V ≤ VIC ≤ 3 V4248dBA
Input impedance differential modeVCM = 0 V20 || 2.3kΩ || pFC
Input impedance common modeVCM = 0 V20 || 2.3kΩ || pFC
OUTPUT(6)
Output voltage headroom to either supplyTJ ≈ 25°C1.41.51.75VA
TJ = –40°C to +85°C1.95VB
Output current drive±0.8 VPP, RLOAD = 20 Ω±35±45mAA
DC output impedanceLoad current = ±20 mA0.3ΩC
POWER SUPPLY (D2S + Midsupply Buffer Only; OPS Disabled: DISABLE pin ≥ 1.3 V)
Supply current±6-V supplies20.221.326mAA
Supply current temperature coefficient8µA/°CC
Positive power-supply rejection ratio (+PSRR)Referred to input6271dBA
Negative power-supply rejection ratio (–PSRR)Referred to input6171dBA
Test levels (all values set by characterization and simulation): (A) 100% tested at TA≈ TJ≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. DC limits tested with no self-heating. Add internal self heating to TA for TJ.
This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √ 2) × 2π × f–3dB.
Currents out of pin treated as a positive polarity.
Applies to input pins 2 (IN+) and 3 (IN–).
Output measured at pin 6.
Output measured at pin 6.