This optional block can be completely unconnected and not used if the design does not require this feature. Internal 50 kΩ resistors to the power supplies bias the input of the buffer to the midpoint of the supplies used. The internal resistors set a midsupply operating point when the buffer is not used, as well as a default midsupply point at the buffer output to be used in other stages for single-supply, ac-coupled applications.

The buffer provides a very wideband, low output-impedance when used to drive VREF, pin 14 (see Figure 6-51). To provide this low broadband impedance, the closed-loop midscale (dc) reference buffer offers a very broadband SSBW, but only a modest large-signal bandwidth (LSBW); see Figure 6-49. This path is not normally intended to inject a wideband signal, but can be used for lower-amplitude signals. Driving the buffer output into the VREF pin allows a wideband small-signal term to be added into the D2S along with the signal from the differential inputs.

The midscale (or dc) reference buffer injects an offset voltage to the output offset of the D2S when it drives the VREF pin. The offset has very low drift, but consider the effect of the input bias current times the dc source impedance at VMID_IN (pin 1). When used as a default midsupply reference for single-supply operation, the input to this buffer is just the average of the total power supplies though a 25 kΩ source impedance. Add an external capacitor to filter the supply and the 50 kΩ internal resistors. A 1-µF capacitor on VMID_IN adds a 6-Hz pole to the noise sources. If lower noise at lower frequencies is required, implement a midscale divider with external, lower-valued resistors in parallel with the internal 50 kΩ values.

If the midscale buffer drives the VREF pin, the buffer noise is added to Equation 9 and Equation 10. The midscale buffer 4.4 nV/√ Hz voltage noise is amplified by 0 dB, and adds (RMS) a negligible impact to the total D2S output noise. The biggest impact comes when the internal default 50 kΩ dividers are used. Be sure to decouple VMID_IN with at least a 1 µF capacitor in the application to reduce the noise contribution through this path. Figure 8-5 shows the simulation circuit with the 1 µF capacitor installed. Figure 8-6 shows the simulated output noise for the midscale buffer using the internal 50 kΩ divider with and without the 1 µF capacitor on VMID_IN.

Figure 8-5 Midscale Buffer Noise Model

Figure 8-6 Buffer-Output Noise Comparison With and Without the 1 µF Bypass Capacitor on VMID_IN

In the flat region, the 1 µF capacitor reduces the midscale buffer output spot noise from approximately 55 nV/√ Hz to 4.4 nV/√ Hz. If the noise below 100 Hz is unacceptable, either add a low-noise buffer to drive this input, or add lower-value resistors externally to set up the midsupply bias. Also, consider the noise impact of any reference voltage source driving the midscale buffer path.