SBOS778D April   2016  – April 2021 THS4551


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Companion Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Open-Loop Gain and Output Impedance
      2. 9.3.2 Setting Resistor Values Versus Gain
      3. 9.3.3 I/O Headroom Considerations
      4. 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 9.4.2 Operation from a Differential Input to a Differential Output
        1. AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 9.4.3 Input Overdrive Performance
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Noise Analysis
      2. 10.1.2 Factors Influencing Harmonic Distortion
      3. 10.1.3 Driving Capacitive Loads
      4. 10.1.4 Interfacing to High-Performance Precision ADCs
      5. 10.1.5 Operating the Power Shutdown Feature
      6. 10.1.6 Designing Attenuators
      7. 10.1.7 The Effect of Adding a Feedback Capacitor
    2. 10.2 Typical Applications
      1. 10.2.1 An MFB Filter Driving an ADC Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Analysis
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Example
    3. 12.3 EVM Board
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TINA-TI Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

The Effect of Adding a Feedback Capacitor

Adding a feedback capacitor to band-limit the signal path is very common in lower frequency designs. This approach is very effective for the signal path gain but does create the potential for high-frequency peaking and oscillation for a wideband device such as the THS4551. The feedback capacitor by itself takes the noise gain to 1 V/V at high frequencies. Depending on the frequency where the noise gain goes to 1V/V, and what added phase margin reduction may already be in place resulting from the load RC, the feedback capacitors can cause instability.

Figure 10-7 shows the starting point for a typical band-limited design. At lower frequencies, this example delivers a gain of 10 V/V with an intentional band limit in the feedback RC at 320 kHz. This single 5-V design targets a midsupply output common-mode voltage with only a noise reduction capacitor on the VOCM input control.

GUID-1A381605-368C-4584-AB7A-79CC695B697F-low.gifFigure 10-7 Single-Ended to Differential Stage with a Feedback Pole

The response shape must be probed at the FDA output pins before the added RC pole to the SAR input. Running a wideband sweep with the THS4551 TINA-TI™ model using the SBOC475 simulation file shows a resonance at 50 MHz in Figure 10-8 resulting from the feedback capacitor.

GUID-224C3A0D-C7F3-4205-A8B7-BFFA3CB8D99C-low.gifFigure 10-8 Gain and Phase Plot with a Feedback Pole

One approach to increasing the phase margin when there is a feedback capacitor is to include a differential input capacitor. This approach increases the noise gain at higher frequencies, thus creating a lower-frequency loop gain equal to a 0-dB crossover with more phase margin. Figure 10-9 shows a differential input capacitor equal to the feedback capacitor in the test circuit. This approach increases the noise gain from 1 V/V at higher frequencies (with only a feedback capacitor) to a noise gain of 3 V/V at higher frequencies.

GUID-2D43E368-B936-478D-84F3-6032FBDD0B50-low.gifFigure 10-9 Single-Ended to Differential Stage with a Feedback Pole and Differential Input Capacitor

Re-running the wideband response (using the SBOC474 TINA-TI™ simulation file) simulation illustrates in Figure 10-10 that the resonance is greatly reduced with the higher noise gain at the loop gain equal to a 0-dB crossover at a lower frequency. Although this example is only modestly peaking, good design practice is to include a place for a differential input capacitor (even if not used) for any design using a feedback capacitor across the feedback resistors. This recommendation applies to this simple example and to multiple feedback active filter designs.

GUID-0C519326-29D0-410B-99DA-0121EA7BAEA6-low.gifFigure 10-10 Gain and Phase Plot with a Differential Input Capacitor