Product details

Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.4 BW at Acl (MHz) 150 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 3.3 Iq per channel (typ) (mA) 1.35 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.175 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 45 2nd harmonic (dBc) 128 3rd harmonic (dBc) 139 Frequency of harmonic distortion measurement (MHz) 0.1 GBW (typ) (MHz) 135 Input bias current (max) (pA) 1500000 Features Shutdown CMRR (typ) (dB) 110 Rating Catalog
Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.4 BW at Acl (MHz) 150 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 3.3 Iq per channel (typ) (mA) 1.35 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.175 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 45 2nd harmonic (dBc) 128 3rd harmonic (dBc) 139 Frequency of harmonic distortion measurement (MHz) 0.1 GBW (typ) (MHz) 135 Input bias current (max) (pA) 1500000 Features Shutdown CMRR (typ) (dB) 110 Rating Catalog
VQFN (RGT) 16 9 mm² 3 x 3 VSSOP (DGK) 8 14.7 mm² 3 x 4.9 WQFN (RUN) 10 4 mm² 2 x 2
  • Bandwidth: 150 MHz (G = 1 V/V)
  • Differential Output Slew Rate: 220 V/µs
  • Gain Bandwidth Product: 135 MHz
  • Negative Rail Input (NRI), Rail-to-Rail Output (RRO)
  • Wide Output Common-Mode Control Range
  • Single-Supply Operating Range: 2.7 V to 5.4 V
  • Trimmed-Supply Current: 1.37 mA at 5 V
  • 25°C Input Offset: ±175 µV (max)
  • Input Offset Voltage Drift: ±1.8 µV/°C (max)
  • Differential Input Voltage Noise: 3.3 nV/√ Hz
  • HD2: –128 dBc at 2 VPP, 100 kHz
  • HD3: –139 dBc at 2 VPP, 100 kHz
  • < 50-ns Settling Time: 4-V Step to 0.01%
  • 18-Bit Settling Time: 4-V Step, < 500 ns
  • Bandwidth: 150 MHz (G = 1 V/V)
  • Differential Output Slew Rate: 220 V/µs
  • Gain Bandwidth Product: 135 MHz
  • Negative Rail Input (NRI), Rail-to-Rail Output (RRO)
  • Wide Output Common-Mode Control Range
  • Single-Supply Operating Range: 2.7 V to 5.4 V
  • Trimmed-Supply Current: 1.37 mA at 5 V
  • 25°C Input Offset: ±175 µV (max)
  • Input Offset Voltage Drift: ±1.8 µV/°C (max)
  • Differential Input Voltage Noise: 3.3 nV/√ Hz
  • HD2: –128 dBc at 2 VPP, 100 kHz
  • HD3: –139 dBc at 2 VPP, 100 kHz
  • < 50-ns Settling Time: 4-V Step to 0.01%
  • 18-Bit Settling Time: 4-V Step, < 500 ns

The THS4551 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analog-to-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination.

The THS4551 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output common-mode control supports the ADC running from 1.8-V to 5-V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V.

The THS4551 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 8-pin VSSOP, 16-pin VQFN, and 10-pin WQFN packages.

The THS4551 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analog-to-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination.

The THS4551 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output common-mode control supports the ADC running from 1.8-V to 5-V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V.

The THS4551 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 8-pin VSSOP, 16-pin VQFN, and 10-pin WQFN packages.

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Technical documentation

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Type Title Date
* Data sheet THS4551 Low-Noise, Precision, 150-MHz, Fully Differential Amplifier datasheet (Rev. D) PDF | HTML 23 Apr 2021
Technical article Balancing ADC size, power, resolution and bandwidth in precision data-acquisition systems 03 Dec 2021
Application note Optimizing LCR Meter Front-End Design for Accurate Impedance Measurements PDF | HTML 20 Jan 2021
Application note Setting a Constant Common-Mode Voltage for Fully-Differential SAR ADC Inputs 06 Sep 2019
Circuit design High-input impedance, true differential, AFE attenuator circuit for SAR ADCs (Rev. A) 08 Mar 2019
Circuit design True differential, 4 × 2 MUX, analog front end, simultaneous-sampling ADC circui (Rev. A) 15 Nov 2018
Application note Maximizing System Total Harmonic Distortion Using High Speed Amplifiers 20 Jun 2018
Application note Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs 14 Jun 2018
Circuit design High-current battery monitor circuit: 0–10A, 0-10kHz, 18 bit 22 Dec 2017
Application note Precision Sum Circuit Support Hi Output Current Multiple AFEs in Ultasound App 20 Nov 2017
Technical article Powering up the performance of sensitive test and measurement systems 17 Oct 2017
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mar 2017
Technical article What you need to know about input bias current – and why 08 Dec 2016
Technical article How to minimize filter loss when you drive an ADC 20 Oct 2016
Application note Noise Analysis for High Speed Op Amps (Rev. A) 17 Jan 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS8900BEVM-PDK — ADS8900B Fully-Differential Input, 20-Bit SAR ADC EVM Performance Demonstration Kit (PDK)

The ADS8900B evaluation module (EVM) performance demonstration kit (PDK) is a platform for evaluating the performance of the ADS8900B successive-approximation register (SAR) analog-to-digital converter (ADC), which is a fully-differential input, 20-bit, 1-MSPS device. (...)

User guide: PDF | HTML
Evaluation board

THS4551DGKEVM — THS4551DGK Evaluation Module

The THS4551DGKEVM is an evaluation module for the single THS4551 amplifier in the DGK (VSSOP-8) package. This evaluation module is designed to quickly and easily demonstrate the functionality and versatility of the amplifier. The EVM is ready to connect to power, signal source, and test (...)
User guide: PDF
Not available on TI.com
Evaluation board

THS4551RGTEVM — THS4551RGT Evaluation Module

The THS4551RGTEVM is an evaluation module for the single THS4551 amplifier in the RGT (WQFN-10) package. This evaluation module is designed to quickly and easily demonstrate the functionality and versatility of the amplifier. The EVM is ready to connect to power, signal source, and test (...)
User guide: PDF
Not available on TI.com
Evaluation board

THS4551RUNEVM — THS4551RUN Evaluation Module

The THS4551RUNEVM is an evaluation module for the single THS4551 amplifier in the RUN (WQFN-10) package. This evaluation module is designed to quickly and easily demonstrate the functionality and versatility of the amplifier. The EVM is ready to connect to power, signal source, and test (...)
User guide: PDF
Not available on TI.com
Simulation model

THS4551 PSpice Model (Rev. B)

SBOMB92B.ZIP (53 KB) - PSpice Model
Simulation model

THS4551 TINA-TI Spice Model (Rev. C)

SBOMA28C.TSC (7439 KB) - TINA-TI Spice Model
Simulation model

THS4551DGK Unencrypted TINA-TI Model Package (Rev. C)

SBOMA29C.TSC (35 KB) - TINA-TI Reference Design
Simulation model

TINA-TI 100kHz MFB filter LG test of Figure 87 THS4551

SBOC459.ZIP (80 KB) - TINA-TI Spice Model
Simulation model

TINA-TI AC Coupled Single to Differentiate Gain of 2 Figure70 THS4551

SBOC460.ZIP (147 KB) - TINA-TI Spice Model
Simulation model

TINA-TI AC coupled different IO Figure 75 THS4551

SLOC341.ZIP (107 KB) - TINA-TI Spice Model
Simulation model

TINA-TI ADTL1-4-75 Model Test for Figure 62 THS4551

SBOC463.ZIP (198 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Attenuator With No Caps Gain of 0.1 Figure80 THS4551

SBOC465.ZIP (201 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Attenuator With a Caps Gain of 0.1 Figure81 THS4551

SBOC464.ZIP (199 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Basic Gain of 1 Test Circuit Figure61 THS4551

SBOC466.ZIP (228 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Common Mode Test CKT Figure65 THS4551

SBOC467.ZIP (118 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Differential Audio DAC ZT Design Figure90 THS4551

SBOC468.ZIP (87 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Differential IO with OPA2192 to FDA to SAR Figure 76 THS4551

SBOC469.ZIP (118 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Differential Transimpedance LG Sim Figure90 THS4551

SBOC470.ZIP (10 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter Figure87 THS4551

SBOC471.ZIP (171 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Gain of 5 Single to Different Simplified for Figure72 THS4551

SBOC472.ZIP (89 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Gain of 5 Single to Different with 10Mhz Bessel Figure93 THS4551

SBOC473.ZIP (218 KB) - TINA-TI Spice Model
Simulation model

TINA-TI High Gain Single to Different with Feedback Pole Figure 83 THS4551

SBOC475.ZIP (117 KB) - TINA-TI Spice Model
Simulation model

TINA-TI High Gain Single to Different with Feedback Pole and Input C Figure 85

SBOC474.ZIP (101 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Open Loop No Load Response Figure99 THS4551

SBOC476.ZIP (68 KB) - TINA-TI Spice Model
Simulation model

TINA-TI Single to Differential Attenuator Figure71 THS4551

SBOC477.ZIP (119 KB) - TINA-TI Spice Model
Calculation tool

TI FDA Calculator

SBOR022.ZIP (1639 KB)
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF

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VQFN (RGT) 16 View options
VSSOP (DGK) 8 View options
WQFN (RUN) 10 View options

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