SLVSO96 October   2026 TICS100MOD

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Resistance Characteristics
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystem
      1. 7.2.1 Arm Cortex-R5F Subsystem
    3. 7.3 Identification
  9. 8 Application Information
    1. 8.1 Typical Application
    2. 8.2 Reset
    3. 8.3 Boot Modes
    4. 8.4 LED Indicators
    5. 8.5 Thermal Considerations
    6. 8.6 PCB Layout Recommendations
    7. 8.7 Protocol Support Details
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Device Nomenclature Boilerplate
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
  12. 11Revision History

Package Options

Mechanical Data (Package|Pins)
  • 0|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Resistance Characteristics

It is recommended to perform thermal simulations at the system level with the worst-case device power consumption.
PARAMETER DESCRIPTION ℃/W(1)(2) AIR FLOW (m/s)(3)
RΘJC Junction-to-case 7.1 N/A
RΘJB Junction-to-board 6.7 N/A
RΘJA Junction-to-free air 20.7 0
RΘJA Junction-to-moving air 14.5 1
13.3 2
12.6 3
ΨJT Junction-to-package top 0.14 0
0.40 1
0.53 2
0.64 3
ΨJB Junction-to-board 6.5 0
6.0 1
5.9 2
5.9 3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) ℃/W = degrees Celsius per watt
(3) m/s = meters per second