SBOS833R Data sheet

SBOS833R October 2017 – November 2021 TLV9001 , TLV9002 , TLV9004

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DPW|5
DBV|5
DBV|6
DCK|5
DCK|6

Thermal pad, mechanical data (Package|Pins)

DPW|5
- QFND567C
DCK|5
- QFND228B
DCK|6
- QFND228B

Orderable Information

7.11 Typical Characteristics

at T_A = 25°C, V+ = 2.75 V, V– = –2.75 V, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2 (unless otherwise noted)

V_S = 5 V

Figure 7-1 Offset Voltage Distribution Histogram

Figure 7-3 Input Offset Voltage vs Temperature

Figure 7-5 Offset Voltage vs Supply Voltage

Figure 7-7 I_B and I_OS vs Common-Mode Voltage

C_L = 10 pF

Figure 7-9 Open-Loop Gain and Phase vs Frequency

C_L = 10 pF

Figure 7-11 Closed-Loop Gain vs Frequency

Figure 7-13 PSRR vs Frequency

Figure 7-15 CMRR vs Frequency

Figure 7-17 0.1-Hz to 10-Hz Integrated Voltage Noise

V_S = 5.5 V	V_CM = 2.5 V	G = 1
BW = 80 kHz	V_OUT = 0.5 V_RMS

Figure 7-19 THD + N vs Frequency

Figure 7-21 Quiescent Current vs Supply Voltage

Figure 7-23 Open-Loop Output Impedance vs Frequency

G = –1	V_IN = 100 mVpp

Figure 7-25 Small Signal Overshoot vs Capacitive Load

G = 1	V_IN = 6.5 V_PP

Figure 7-27 No Phase Reversal

G = 1	V_IN = 100 mV_PP	C_L = 10 pF

Figure 7-29 Small-Signal Step Response

G = 1

C_L = 100 pF

2-V step

Figure 7-31 Large-Signal Settling Time (Negative)

Figure 7-33 Short-Circuit Current vs Temperature

Figure 7-35 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

V_S = 5 V, T_A = –40°C to 125°C

Figure 7-2 Offset Voltage Drift Distribution Histogram

Figure 7-4 Offset Voltage vs Common-Mode

Figure 7-6 I_B and I_OS vs Temperature

Figure 7-8 Open-Loop Gain vs Temperature

Figure 7-10 Open-Loop Gain vs Output Voltage

Figure 7-12 Output Voltage vs Output Current (Claw)

V_S = 1.8 V to 5.5 V

Figure 7-14 DC PSRR vs Temperature

	V_CM = (V–) – 0.1 V to (V+) – 1.4 V

Figure 7-16 DC CMRR vs Temperature

Figure 7-18 Input Voltage Noise Spectral Density

V_S = 5.5 V	V_CM = 2.5 V	ƒ = 1 kHz
G = 1	BW = 80 kHz

Figure 7-20 THD + N vs Amplitude

Figure 7-22 Quiescent Current vs Temperature

G = 1	V_IN = 100 mVpp

Figure 7-24 Small Signal Overshoot vs Capacitive Load

Figure 7-26 Phase Margin vs Capacitive Load

G = –10	V_IN = 600 mV_PP

Figure 7-28 Overload Recovery

G = 1	V_IN = 4 V_PP	C_L = 10 pF

Figure 7-30 Large-Signal Step Response

G = 1

C_L = 100 pF

2-V step

Figure 7-32 Large-Signal Settling Time (Positive)

Figure 7-34 Maximum Output Voltage vs Frequency

Figure 7-36 Channel Separation