The C6745/6747 device includes two choices to provide an external clock input, which is fed to the on-chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended. Typical load capacitance values are 10-20 pF, where the load capacitance is the series combination of C1 and C2.
The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1, the internal oscillator is disabled.
|fosc||Oscillator frequency range (OSCIN/OSCOUT)||12||30||MHz|
|fOSCIN||OSCIN frequency range (OSCIN)||12||50||MHz|
|tc(OSCIN)||Cycle time, external clock driven on OSCIN||20||ns|
|tw(OSCINH)||Pulse width high, external clock on OSCIN||0.4 tc(OSCIN)||ns|
|tw(OSCINL)||Pulse width low, external clock on OSCIN||0.4 tc(OSCIN)||ns|
|tt(OSCIN)||Transition time, OSCIN||0.25P or 10 (1)||ns|
|tj(OSCIN)||Period jitter, OSCIN||0.02P||ns|