The Programmable Real-Time Unit Subsystem (PRUSS) consists of
The two PRUs can operate completely independently or in coordination with each other. The PRUs can also work in coordination with the device level host CPU. This is determined by the nature of the program which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory mapped data structures, handling of system events that have tight realtime constraints and interfacing with systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single 64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR) of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is documented in Table 6-105 and in Table 6-106. Note that these two memory maps are implemented inside the PRUSS and are local to the components of the PRUSS.
|0x0000 0000 - 0x0000 0FFF||PRU0 Instruction RAM||PRU1 Instruction RAM|
|0x0000 0000 - 0x0000 01FF||Data RAM 0 (1)||Data RAM 1 (1)|
|0x0000 0200 - 0x0000 1FFF||Reserved||Reserved|
|0x0000 2000 - 0x0000 21FF||Data RAM 1 (1)||Data RAM 0 (1)|
|0x0000 2200 - 0x0000 3FFF||Reserved||Reserved|
|0x0000 4000 - 0x0000 6FFF||INTC Registers||INTC Registers|
|0x0000 7000 - 0x0000 73FF||PRU0 Control Registers||PRU0 Control Registers|
|0x0000 7400 - 0x0000 77FF||Reserved||Reserved|
|0x0000 7800 - 0x0000 7BFF||PRU1 Control Registers||PRU1 Control Registers|
|0x0000 7C00 - 0xFFFF FFFF||Reserved||Reserved|
The global view of the PRUSS internal memories and control ports is documented in Table 6-107. The offset addresses of each region are implemented inside the PRUSS but the global device memory mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and PRU1 can use either the local or global addresses to access their internal memories, but using the local addresses will provide access time several cycles faster than using the global addresses. This is because when accessing via the global address the access needs to be routed through the switch fabric outside PRUSS and back in through the PRUSS slave port.
|0x01C3 0000 - 0x01C3 01FF||Data RAM 0|
|0x01C3 0200 - 0x01C3 1FFF||Reserved|
|0x01C3 2000 - 0x01C3 21FF||Data RAM 1|
|0x01C3 2200 - 0x01C3 3FFF||Reserved|
|0x01C3 4000 - 0x01C3 6FFF||INTC Registers|
|0x01C3 7000 - 0x01C3 73FF||PRU0 Control Registers|
|0x01C3 7400 - 0x01C3 77FF||PRU0 Debug Registers|
|0x01C3 7800 - 0x01C3 7BFF||PRU1 Control Registers|
|0x01C3 7C00 - 0x01C3 7FFF||PRU1 Debug Registers|
|0x01C3 8000 - 0x01C3 8FFF||PRU0 Instruction RAM|
|0x01C3 9000 - 0x01C3 BFFF||Reserved|
|0x01C3 C000 - 0x01C3 CFFF||PRU1 Instruction RAM|
|0x01C3 D000 - 0x01C3 FFFF||Reserved|
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and configuration registers) using the global memory space addresses.