SPRS377F September   2008  – June 2014 TMS320C6745 , TMS320C6747

PRODUCTION DATA.  

  1. 1TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6747 Top Level Memory Map
      2. Table 3-5 C6745 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (only SDRAM)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13 Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17 Ethernet Media Access Controller (EMAC)
      18. 3.6.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20 General Purpose Input Output (GPIO)
      21. 3.6.21 Reserved and No Connect
      22. 3.6.22 Supply and Ground
      23. 3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-9  Timing Requirements for GPIO Inputs (see )
        2. Table 6-10 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-11 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface A (EMIFA) Registers
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA SDRAM Interface Timing Requirements
        2. Table 6-20 EMIFA SDRAM Interface Switching Characteristics
        3. Table 6-21 EMIFA Asynchronous Memory Timing Requirements
        4. Table 6-22 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-26 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-27 EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature Range
        3. Table 6-28 EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive Temperature Ranges
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-32 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-33 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-41 Timing Requirements for MDIO Input (see and )
        2. Table 6-42 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 McASP0 Timing Requirements
          2. Table 6-48 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-49 McASP1 Timing Requirements
          2. Table 6-50 McASP1 Switching Characteristics
        3. 6.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
          1. Table 6-51 McASP2 Timing Requirements
          2. Table 6-52 McASP2 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-54 General Timing Requirements for SPI0 Master Modes
          2. Table 6-55 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-56 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-57 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-58 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-59 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-60 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-61 Additional SPI0 Slave Timings, 5-Pin Option
          9. Table 6-62 General Timing Requirements for SPI1 Master Modes
          10. Table 6-63 General Timing Requirements for SPI1 Slave Modes
          11. Table 6-64 Additional SPI1 Master Timings, 4-Pin Enable Option
          12. Table 6-65 Additional SPI1 Master Timings, 4-Pin Chip Select Option
          13. Table 6-66 Additional SPI1 Master Timings, 5-Pin Option
          14. Table 6-67 Additional SPI1 Slave Timings, 4-Pin Enable Option
          15. Table 6-68 Additional SPI1 Slave Timings, 4-Pin Chip Select Option
          16. Table 6-69 Additional SPI1 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-71 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-72 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-74 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-75 eQEP Switching Characteristics
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-77 eHRPWM Timing Requirements
        2. Table 6-78 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 LCD Controller
      1. 6.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.21.2 LCD Raster Mode
        1. Table 6-84 LCD Raster Mode Timing
    22. 6.22 Timers
      1. 6.22.1 Timer Electrical Data/Timing
        1. Table 6-86 Timing Requirements for Timer Input (see )
        2. Table 6-87 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    23. 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.23.1 I2C Device-Specific Information
      2. 6.23.2 I2C Peripheral Registers Description(s)
      3. 6.23.3 I2C Electrical Data/Timing
        1. 6.23.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-89 I2C Input Timing Requirements
          2. Table 6-90 I2C Switching Characteristics
    24. 6.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.24.1 UART Peripheral Registers Description(s)
      2. 6.24.2 UART Electrical Data/Timing
        1. Table 6-92 Timing Requirements for UARTx Receive (see )
        2. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    25. 6.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1
      2. 6.25.1     USB1 Unused Signal Configuration
    26. 6.26 USB0 OTG (USB2.0 OTG)
      1. 6.26.1 USB2.0 Electrical Data/Timing
        1. Table 6-97 Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see )
      2. 6.26.2 USB0 Unused Signal Configuration
    27. 6.27 Host-Port Interface (UHPI)
      1. 6.27.1 HPI Device-Specific Information
      2. 6.27.2 HPI Peripheral Register Description(s)
      3. 6.27.3 HPI Electrical Data/Timing
        1. Table 6-99  Timing Requirements for Host-Port Interface Cycles
        2. Table 6-100 Switching Characteristics for Host-Port Interface Cycles
    28. 6.28 Power and Sleep Controller (PSC)
      1. 6.28.1 Power Domain and Module Topology
        1. 6.28.1.1 Power Domain States
        2. 6.28.1.2 Module States
    29. 6.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.29.1 PRUSS Register Descriptions
    30. 6.30 Emulation Logic
      1. 6.30.1 JTAG Port Description
      2. 6.30.2 Scan Chain Configuration Parameters
      3. 6.30.3 JTAG 1149.1 Boundary Scan Considerations
    31. 6.31 IEEE 1149.1 JTAG
      1. 6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
      2. 6.31.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-115 Timing Requirements for JTAG Test Port (see )
        2. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
    32. 6.32 Real Time Clock (RTC)
      1. 6.32.1 Clock Source
      2. 6.32.2 Real-Time Clock Registers
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Related Links
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.12 Memory Protection Units

The MPU performs memory protection checking. It receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. If allowed, the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails the protection check) then the MPU does not pass the transfer to the output bus but rather services the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as well as generating an interrupt about the fault. The following features are supported by the MPU:

  • Provides memory protection for fixed and programmable address ranges
  • Supports multiple programmable address region
  • Supports secure and debug access privileges
  • Supports read, write, and execute access privileges
  • Supports privid(8) associations with ranges
  • Generates an interrupt when there is a protection violation, and saves violating transfer parameters
  • MMR access is also protected

Table 6-29 MPU1 Configuration Registers

MPU1
BYTE ADDRESS		 ACRONYM REGISTER DESCRIPTION
0x01E1 4000 REVID Revision ID
0x01E1 4004 CONFIG Configuration
0x01E1 4010 IRAWSTAT Interrupt raw status/set
0x01E1 4014 IENSTAT Interrupt enable status/clear
0x01E1 4018 IENSET Interrupt enable
0x01E1 401C IENCLR Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF - Reserved
0x01E1 4200 PROG1_MPSAR Programmable range 1, start address
0x01E1 4204 PROG1_MPEAR Programmable range 1, end address
0x01E1 4208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 420C - 0x01E1 420F - Reserved
0x01E1 4210 PROG2_MPSAR Programmable range 2, start address
0x01E1 4214 PROG2_MPEAR Programmable range 2, end address
0x01E1 4218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 421C - 0x01E1 421F - Reserved
0x01E1 4220 PROG3_MPSAR Programmable range 3, start address
0x01E1 4224 PROG3_MPEAR Programmable range 3, end address
0x01E1 4228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 422C - 0x01E1 422F - Reserved
0x01E1 4230 PROG4_MPSAR Programmable range 4, start address
0x01E1 4234 PROG4_MPEAR Programmable range 4, end address
0x01E1 4238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 423C - 0x01E1 423F - Reserved
0x01E1 4240 PROG5_MPSAR Programmable range 5, start address
0x01E1 4244 PROG5_MPEAR Programmable range 5, end address
0x01E1 4248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 424C - 0x01E1 424F - Reserved
0x01E1 4250 PROG6_MPSAR Programmable range 6, start address
0x01E1 4254 PROG6_MPEAR Programmable range 6, end address
0x01E1 4258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 425C - 0x01E1 42FF - Reserved
0x01E14300 FLTADDRR Fault address
0x01E1 4304 FLTSTAT Fault status
0x01E1 4308 FLTCLR Fault clear
0x01E1 430C - 0x01E1 4FFF - Reserved

Table 6-30 MPU2 Configuration Registers

MPU2
BYTE ADDRESS		 ACRONYM REGISTER DESCRIPTION
0x01E1 5000 REVID Revision ID
0x01E1 5004 CONFIG Configuration
0x01E1 5010 IRAWSTAT Interrupt raw status/set
0x01E1 5014 IENSTAT Interrupt enable status/clear
0x01E1 5018 IENSET Interrupt enable
0x01E1 501C IENCLR Interrupt enable clear
0x01E1 5020 - 0x01E1 50FF - Reserved
0x01E1 5100 FXD_MPSAR Fixed range start address
0x01E1 5104 FXD_MPEAR Fixed range end start address
0x01E1 5108 FXD_MPPA Fixed range memory page protection attributes
0x01E1 510C - 0x01E1 51FF - Reserved
0x01E1 5200 PROG1_MPSAR Programmable range 1, start address
0x01E1 5204 PROG1_MPEAR Programmable range 1, end address
0x01E1 5208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 520C - 0x01E1 520F - Reserved
0x01E1 5210 PROG2_MPSAR Programmable range 2, start address
0x01E1 5214 PROG2_MPEAR Programmable range 2, end address
0x01E1 5218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 521C - 0x01E1 521F - Reserved
0x01E1 5220 PROG3_MPSAR Programmable range 3, start address
0x01E1 5224 PROG3_MPEAR Programmable range 3, end address
0x01E1 5228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 522C - 0x01E1 522F - Reserved
0x01E1 5230 PROG4_MPSAR Programmable range 4, start address
0x01E1 5234 PROG4_MPEAR Programmable range 4, end address
0x01E1 5238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 523C - 0x01E1 523F - Reserved
0x01E1 5240 PROG5_MPSAR Programmable range 5, start address
0x01E1 5244 PROG5_MPEAR Programmable range 5, end address
0x01E1 5248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 524C - 0x01E1 524F - Reserved
0x01E1 5250 PROG6_MPSAR Programmable range 6, start address
0x01E1 5254 PROG6_MPEAR Programmable range 6, end address
0x01E1 5258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 525C - 0x01E1 525F - Reserved
0x01E1 5260 PROG7_MPSAR Programmable range 7, start address
0x01E1 5264 PROG7_MPEAR Programmable range 7, end address
0x01E1 5268 PROG7_MPPA Programmable range 7, memory page protection attributes
0x01E1 526C - 0x01E1 526F - Reserved
0x01E1 5270 PROG8_MPSAR Programmable range 8, start address
0x01E1 5274 PROG8_MPEAR Programmable range 8, end address
0x01E1 5278 PROG8_MPPA Programmable range 8, memory page protection attributes
0x01E1 527C - 0x01E1 527F - Reserved
0x01E1 5280 PROG9_MPSAR Programmable range 9, start address
0x01E1 5284 PROG9_MPEAR Programmable range 9, end address
0x01E1 5288 PROG9_MPPA Programmable range 9, memory page protection attributes
0x01E1 528C - 0x01E1 528F - Reserved
0x01E1 5290 PROG10_MPSAR Programmable range 10, start address
0x01E1 5294 PROG10_MPEAR Programmable range 10, end address
0x01E1 5298 PROG10_MPPA Programmable range 10, memory page protection attributes
0x01E1 529C - 0x01E1 529F - Reserved
0x01E1 52A0 PROG11_MPSAR Programmable range 11, start address
0x01E1 52A4 PROG11_MPEAR Programmable range 11, end address
0x01E1 52A8 PROG11_MPPA Programmable range 11, memory page protection attributes
0x01E1 52AC - 0x01E1 52AF - Reserved
0x01E1 52B0 PROG12_MPSAR Programmable range 12, start address
0x01E1 52B4 PROG12_MPEAR Programmable range 12, end address
0x01E1 52B8 PROG12_MPPA Programmable range 12, memory page protection attributes
0x01E1 52BC - 0x01E1 52FF - Reserved
0x01E1 5300 FLTADDRR Fault address
0x01E1 5304 FLTSTAT Fault status
0x01E1 5308 FLTCLR Fault clear
0x01E1 530C - 0x01E1 5FFF - Reserved