The C6745/6747 DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8.
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the OSCIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-9 illustrates the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the DSP to run from the PLL by setting PLLEN = 1.
|1||PLLRST: Assertion time during initialization||N/A||1000||N/A||ns|
|2||Lock time: The time that the application has to wait for the PLL to acquire locks before setting PLLEN, after changing PREDIV, PLLM, or OSCIN||N/A||N/A||OSCIN
|4||PLL input frequency
|12||30 (if internal oscillator is used)
50 (if external clock source is used)
|5||PLL multiplier values (PLLM) (1)||x20||x4||x32|
|6||PLL output frequency. ( PLLOUT )||N/A||300||600||MHz|