SCDS487A October   2025  – December 2025 TMUX4819 , TMUX4821

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Absolute Maximum Ratings
  7. ESD Ratings
  8. Thermal Information
  9. Recommended Operating Conditions
  10. Source or Drain Continuous Current
  11. 10Source or Drain RMS Current
  12. 11Electrical Characteristics 
  13. 12Switching Characteristics 
  14. 13Typical Characteristics
  15. 14Parameter Measurement Information
    1. 14.1  On-Resistance
    2. 14.2  On-Leakage Current
    3. 14.3  Off-Leakage Current
    4. 14.4  Power-Off Leakage Current
    5. 14.5  Propagation Delay
    6. 14.6  tON (VDD) and tOFF (VDD) Time
    7. 14.7  Transition Time
    8. 14.8  Break-Before-Make
    9. 14.9  THD + Noise
    10. 14.10 Power Supply Rejection Ratio (PSRR)
    11. 14.11 Charge Injection
    12. 14.12 Bandwidth
    13. 14.13 Off Isolation
    14. 14.14 Crosstalk
  16. 15Detailed Description
    1. 15.1 Functional Block Diagram
    2. 15.2 Device Functional Modes
    3. 15.3 Feature Description
      1. 15.3.1 Beyond the Supply
      2. 15.3.2 Bidirectional Operation
      3. 15.3.3 Power-Off Protection
      4. 15.3.4 1.2V and 1.8V Logic Compatible Inputs
      5. 15.3.5 Integrated Pull-Down Resistor on Logic Pins
      6. 15.3.6 Fail-Safe Logic
  17. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Audio Amplifier Switching
        1. 16.2.1.1 Design Requirements
        2. 16.2.1.2 Detailed Design Procedure
        3. 16.2.1.3 Application Curves
      2. 16.2.2 Smart Drug Delivery Flow Meters
        1. 16.2.2.1 Design Requirements
        2. 16.2.2.2 Detailed Design Procedure
        3. 16.2.2.3 Application Curve
    3. 16.3 Power Supply Recommendations
    4. 16.4 Layout
      1. 16.4.1 Layout Guidelines
      2. 16.4.2 Layout Example
  18. 17Device and Documentation Support
    1. 17.1 Documentation Support
      1. 17.1.1 Related Documentation
    2. 17.2 Receiving Notification of Documentation Updates
    3. 17.3 Support Resources
    4. 17.4 Trademarks
    5. 17.5 Electrostatic Discharge Caution
    6. 17.6 Glossary
  19. 18Revision History
  20. 19Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self-inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 16-6 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.

TMUX4821 TMUX4819 Trace
                    ExampleFigure 16-6 Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies.

Some key considerations are as follows:

  • For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND. TI recommends a 0.1µF and 1µF capacitor, placing the lowest value capacitor as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
  • Keep the input lines as short as possible.
  • Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.
  • Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground planes.