The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges C_BULK, C_VCC, C_VB and C_VBG while the PD is unpowered. Thus V_VDD-RTN will be a small voltage until just after full voltage is applied to the PD, as seen in Figure 8-7.

The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When V_VDD rises above the UVLO turnon threshold (V_UVLO-R, approximately 37.6 V) with RTN high, the TPS23730 enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-9 for an example. Converter switching is disabled while C_BULK charges and V_RTN falls from V_VDD to nearly V_VSS; however, the converter start-up circuit is allowed to charge C_VCC (the VB regulator also powers the internal converter circuits as V_VCC rises). Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to the operational level (approximately 1.85 A). Additionally, once the inrush period duration has also exceeded approximately 84 ms (end of inrush phase), the converter switching is allowed to start, once V_VCC also goes above its UVLO (approximately 8.25 V).

Continuing the start-up sequence shown in Figure 8-9, once V_VCC goes above its UVLO , the soft-start (SST) capacitor is first discharged with controlled current (I_SSD) below nominally 0.2 V (V_SFST) if the discharge was not already completed, then it is gradually recharged until it reaches ~0.25 V (V_SSOFS in closed-loop mode) at which point the converter switching is enabled, following the closed loop controlled soft-start sequence. Note that the startup current source capability is such that it can fully maintain V_VCC during the converter soft-start without requiring any significant C_VCC capacitance, in 48 V input applications. At the end of the soft-start period, more specifically when SST voltage has exceeded ~2 V (V_STUOF), the startup current source is turned off. V_VCC falls as it powers the internal circuits including the switching MOSFET gate. If the converter control-bias output rises to support V_VCC before it falls to V_{CUVLO_F} (~6.1 V), a successful start-up occurs. Figure 8-9 shows a small droop in V_VCC while the output voltage rises smoothly and a successful start-up occurs.

Figure 8-10 also illustrates similar scenario if optocoupler feedback is used instead of PSR. In this case, the converter switching is enabled when V_SST exceeds approximately 0.6 V (V_SSOFS in peak current mode).

Figure 8-9 Power Up and Start - Flyback with PSR

Figure 8-10 Power Up and Start - with Opto Feedback

The converter shuts off when V_VCC falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns off. A restart initiates if the converter turns off and there is sufficient VDD voltage. This type of operation is sometimes referred to as hiccup mode, which when combined with the soft-start provides robust output short protection by providing time-average heating reduction of the output rectifier.

Figure 8-11 illustrates the situation when there is severe overload at the main output which causes VCC hiccup. After VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start cycle is reinitiated, the soft-start capacitor being first discharged with controlled current, introducing a short pause before the output voltage is ramped up.

Figure 8-11 Restart Following Severe Overload at Main Output of PSR Flyback DC-DC Converter

Also, when a VCC fall occurs, the TPS23730 can differentiate between an overload and a light load condition. For example a diode-rectified flyback with optocoupled feedback may have its VCC rail to fall in situation of light load due to temporary switching stop. In this case, the output voltage has to be maintained and a soft-start would not be acceptable. To address this case, if V_VCC falls below approximately 7.1 V due to light load, the TPS23730 turns back on the startup immediately and for a short period of time to bring VCC voltage back up, and there is no soft-start recycling.

Figure 8-12 Startup Operation if VCC Undervoltage is caused by Light Load Condition of Diode-rectified Flyback DC-DC Converter

If V_VDD-VSS drops below the lower PoE UVLO (V_{UVLO_F}, approximately 32 V), the hotswap MOSFET is turned off, but the converter still runs (unless LINEUV input is pulled low). The converter stops if V_VCC falls below the V_{CUVLO_F} (~6.1 V), the hotswap is in inrush current limit, the SST pin is pulled to ground, or the converter is in thermal shutdown.