SLVSGY2 October   2023 TPS2HCS10-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Programmable Fuse Protection
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Overcurrent Protection And Capacitive Load Charging
        4. 8.3.1.4 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Channel Output (FET) Enabled
          2. 8.3.2.1.2 Detection With Channel Output Disabled
        2. 8.3.2.2 Digital Current Sense Output
          1. 8.3.2.2.1 RSNS Value and Accuracy / Resolution of Current Measurement
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Output Voltage and FET Temperature Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 SLEEP
      3. 8.4.3 CONFIG/ACTIVE
      4. 8.4.4 Battery Supply Input (VBB) Under-voltage
      5. 8.4.5 LOW POWER MODE (LPM) State
      6. 8.4.6 LIMP HOME state
      7. 8.4.7 SPI Mode Operation
    5. 8.5 TPS2HC10S Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

TPS2HC10S Registers

Table 8-5 lists the memory-mapped registers for the TPS2HC10S registers. All register offset addresses not listed in Table 8-5 should be considered as reserved locations and the register contents should not be modified.

Table 8-5 TPS2HC10S Registers
OffsetAcronymRegister NameSection
1hCRC_CONFIGConfigure CRCGo
2hSLEEPSets to go into SLEEP sate from ACTIVE or STANDBY stateGo
3hLPMSets to go in or out of Low power mode (LPM STATE)Go
4hCH_FLT_TYPE_FAULT_GLOBAL_TYPEFaults for any channel and global faultsGo
5hFAULT_MASKMask the reporting of the faults on the fault pinGo
6hABIST_RESULTABIST Diagniostic resultGo
7hSW_STATETurn on/off OUTxGo
8hDEVICE_SAFDevice BIST, LIMPHOME, and locking set by SPIGo
9hDEV_CONFIGDevice Configureable settings registerGo
AhADC_CONFIGADC configuration - disable ADC conversions or ADC entirelyGo
BhADC_RESULT_VBBADC conversion result VBBGo
DhFLT_STAT_CH1Status of the channels and channel faultsGo
EhPWM_CH1Set all PWM configurations for channel 1Go
FhILIM_CONFIG_CH1Set all current limit configuration for channel 1Go
10hDIAG_CONFIG_CH1Configuration register for channel 1Go
11hADC_RESULT_CH1_IADC conversion result load current sense CH1Go
12hADC_RESULT_CH1_TADC conversion result TJ sense CH1Go
13hADC_RESULT_CH1_VADC conversion result VOUT sense CH1Go
14hI2T_CONFIG_CH1Set all I2T configuration bitsGo
15hFLT_STAT_CH2Status of the channels and channel faultsGo
16hPWM_CH2Set all PWM configurations for channel 2Go
17hILIM_CONFIG_CH2Set all current limit configuration for channel 2Go
18hDIAG_CONFIG_CH2Configuration register for channel 2Go
19hADC_RESULT_CH2_IADC conversion result load current sense CH2Go
1AhADC_RESULT_CH2_TADC conversion result TJ sense CH2Go
1BhADC_RESULT_CH2_VADC conversion result VOUT sense CH2Go
1ChI2T_CONFIG_CH2Set all I2T configuration bitsGo

Complex bit access types are encoded to fit into small table cells. Table 8-6 shows the codes that are used for access types in this section.

Table 8-6 TPS2HC10S Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C
Write
1 to clear
WCW
C
Write
to Clear
Reset or Default Value
-nValue after reset or the default value

8.5.1 CRC_CONFIG Register (Offset = 1h) [Reset = 0000h]

CRC_CONFIG is shown in Table 8-7.

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Table 8-7 CRC_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0h Reserved
0CRC_ENR/W0h Set this bit to 1 to enable CRC check of SPI command frame.
0h = No CRC check of SPI command frame
1h = CRC check of SPI command frame enabled

8.5.2 SLEEP Register (Offset = 2h) [Reset = 0000h]

SLEEP is shown in Table 8-8.

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Table 8-8 SLEEP Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0h Reserved
0SLEEPR/W0h Setting this bit to 1 puts the device into SLEEP mode where everything shuts off

8.5.3 LPM Register (Offset = 3h) [Reset = 0000h]

LPM is shown in Table 8-9.

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Table 8-9 LPM Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8-7RESERVEDR0h Reserved
6-5RESERVEDR0h Reserved
4-3LPM_EXIT_CURR_CH2R/W0h Set the threshold for exit from LPM mode due to load current increase - CH2.
0h = 600 mA
1h = 800 mA
2h = 200 mA
3h = 400 mA
2-1LPM_EXIT_CURR_CH1R/W0h Set the threshold for exit from LPM mode due to load current increase - CH1.
0h = 600 mA
1h = 800 mA
2h = 200 mA
3h = 400 mA
0LPMR/W0h Setting this bit to 1 puts the device into LPM mode with the channels enabled as per the device

8.5.4 CH_FLT_TYPE_FAULT_GLOBAL_TYPE Register (Offset = 4h) [Reset = 0347h]

CH_FLT_TYPE_FAULT_GLOBAL_TYPE is shown in Table 8-10.

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Table 8-10 CH_FLT_TYPE_FAULT_GLOBAL_TYPE Register Field Descriptions
BitFieldTypeResetDescription
15I2T_FLTR0h The bit is set if there is a I2T fault due to ovecurrent in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists.
14LPM_FLTR0h The bit is set if there is a fault during low power mode and the chip comes back to the active state. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists
13CHAN_TSDR0h The bit is set if there is a thermal shutdown fault due to thermal overload in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists.
0h = no thermal shutdown fault in any of the channels
1h = thermal shutdown fault in one of the channels
12ILIMIT_FLTR0h The bit is set if there is a FET turn-off fault due to ovecurrent in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists.
0h = no overcurrent fault in any of the channels
1h = overcurrent fault in one of the channels
11SHRT_VBB_FLTR0h The bit is set if there is a short to VBB supply in the off-state fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists
0h = no off-state short to VBB fault in any of the channels
1h = off-state short to VBB fault in one of the channels
10OL_FLTR0h The bit is set if either there is a wire break in the on or off-state fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists
0h = no on or off-state open laod detection fault in any of the channels
1h = on or off-state open load detection fault in one of the channels
9SUPPLY_FLTR1h The bit is set if either the VDD_UVLO or VBB_UV are faults occur. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists.
0h = no UV fault in VDD, VINT or VBB
1h = UV fault in VDD, VINT or VBB
8GLOBAL_ERR_WRNR1h The bit is set if there is a global fault reported in the FLT_GLOBAL_TYPE register (Bits [7:0] : SPI error, watchdog error, VBB_UV, VBB_UV_WRN, VDD_UVLO, POR fault or LIMPHOME_STAT bit is set. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_GLOBAL_TYPE register is read and the fault condition no longer exists.
0h = no global fault
1h = One of the following errors have occurred: SPI error, watchdog error, VBB_UV, VBB_UV_WRN, VDD_UVLO, POR fault or LIMPHOME_STAT bit is set
7LIMPHOME_STATW1C0h This bit is set high if the device is currently in the limp home mode.
6PORR/WC1h The bit is indicative of whether a power on reset has occurred.
0h = There is no power-on reset anytime after the last register read The register bit is cleared on read, so if read again and the bit is 0, means that no power-on reset has occurred since the read.
1h = A power-on reset has occurred since the last register read.
5RESERVEDR0h Reserved
4SPI_ERRR/WC0h The bit is set if there is an SPI communication error either from format, clock or CRC errors.The fault bit is latched and cleared only after read and the error is removed.
0h = No SPI communication error fault
1h = SPI communication error either from format, clock or CRC has occurred
3WD_ERRR/WC0h The bit is set if the watchdog timer is enabled and there has not been an acceptable SPI command in the watchdog timeout window. The fault bit is latched and cleared only after read and the error is removed.
0h = No SPI interface watchdog error
1h = SPI watchdog timeout error has occurred
2VDD_UVLOR/WC1h The bit is set if VDD supply is below the UVLO threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UVLO condition is removed
0h = No VDD UVLO fault
1h = VDD UVLO fault
1VBB_UV_WRNR/WC1h The bit is set if VBB supply is below the UV warning (UV_WRN) threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UV condition is removed
0h = No VBB UV_WRN fault
1h = VBB UV_WRN fault
0VBB_UVLOR/WC1h The bit is set if VBB supply is below the UV threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UV condition is removed
0h = No VBB UV fault
1h = VBB UV fault

8.5.5 FAULT_MASK Register (Offset = 5h) [Reset = 0000h]

FAULT_MASK is shown in Table 8-11.

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Table 8-11 FAULT_MASK Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR0h Reserved
6MASK_ILIMITR/W0h The bit is set to mask the signaling overcurrent protection fault on the FLT pin
0h = Fault is signaled on the FLT pin on overcurrent FET turn-off occuring
1h = Overcurrent protection fault is not signaled (masked from) on the FLT pin
5MASK_SHRT_VBBR/W0h The bit is set to mask the signaling off-state Short to VBB fault on the FLT pin
0h = Short to VBB Fault is signaled on the FLT pin on detecting the fault with the diagnostic
1h = Short to VBB fault is not signaled (masked from) on the FLT pin
4MASK_OL_OFFR/W0h The bit is set to mask the signaling off-state open load fault on the FLT pin
0h = Off-state wire-break fault is signaled on the FLT pin on detecting the fault with the diagnostic
1h = Off-state wire-break fault is not signaled (masked from) on the FLT pin
3MASK_OL_ONR/W0h The bit is set to mask the signaling on-state open load fault on the FLT pin
0h = On-state wire-break fault is signaled on the FLT pin on detecting the fault with the diagnostic
1h = On-state wire-break fault is not signaled (masked from) on the FLT pin
2MASK_SPI_ERRR/W0h The bit is set to mask the SPI error (SPI_ERR) signaling in the FLT pin output and FAULT_TYPE_STAT register
0h = SPI error is signaled in FAULT_TYPE_STAT register and FLT pin
1h = FAULT_TYPE_STAT register and FLT pin not impacted by SPI error
1MASK_WD_ERRR/W0h The bit is set to mask the SPI watchdog error (WD_ERR) signaling in the FLT pin output and FAULT_TYPE_STAT register
0h = SPI watchdog error is signaled in FAULT_TYPE_STAT register and FLT pin
1h = FAULT_TYPE_STAT register and FLT pin not impacted by SPI watchdog error
0MASK_VBB_UVLOR/W0h The bit is set to mask the supply voltage VBB UVLO fault signaling on the FLT pin output.
0h = VBB UV fault is signaled on the FLT pin on detecting the fault with the diagnostic
1h = VBB UV fault is not signaled (masked from) on the FLT pin

8.5.6 ABIST_RESULT Register (Offset = 6h) [Reset = 0000h]

ABIST_RESULT is shown in Table 8-12.

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Table 8-12 ABIST_RESULT Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0h Reserved
3ADC_GOODR0h This says whether or not the ABIST for the ADC passed (not implemented in the present release)
0h = ABIST for ADC Passed
1h = ABIST for ADC Failed
2ISNS_GOODR0h This says whether or not the ABIST for the ISNS passed (not implemented in the present release)
0h = ABIST for ISNSPassed
1h = ABIST for ISNS Failed
1VBB_UVP_GOODR0h This says whether or not the ABIST for the VBB passed (not implemented in the present release)
0h = ABIST for VBB Passed
1h = ABIST for VBB Failed
0BG_GOODR0h This says whether or not the ABIST for the Bandgap passed (not implemented in the present release)
0h = ABIST for BG Passed
1h = ABIST for BG Failed

8.5.7 SW_STATE Register (Offset = 7h) [Reset = 0000h]

SW_STATE is shown in Table 8-13.

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Table 8-13 SW_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1CH2_ONR/W0h Set this bit to 1 to turn on the FET and CH2 output ON
0h = CH2 Output set to OFF (FET is OFF).
1h = CH2 Output set to ON (FET is ON).
0CH1_ONR/W0h Set this bit to 1 to turn on the FET and CH1 output ON
0h = CH1 Output set to OFF (FET is OFF).
1h = CH1 Output set to ON (FET is ON).

8.5.8 DEVICE_SAF Register (Offset = 8h) [Reset = 0000h]

DEVICE_SAF is shown in Table 8-14.

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Table 8-14 DEVICE_SAF Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12-11RESERVEDR0h Reserved
10-9RESERVEDR0h Reserved
8-7CH2_LH_INR/W0h Decides what to do with the output for LH mode. Either on, off, keep or use associated DI pin
0h = DI control output when in LHM
1h = keep output as it enter LHM
2h = output will be off during LHM
3h = output will be on during LHM
6-5CH1_LH_INR/W0h Decides what to do with the output for LH mode. Either on, off, keep or use associated DI pin
0h = DI control output when in LHM
1h = keep output as it enter LHM
2h = output will be off during LHM
3h = output will be on during LHM
4ADC_ABIST_RUNR/W0h Run the ABIST diaagnostics for the ADC good signal and update the DIAG_RESULT register with the result. Not available in current silicon, but will be in the production version. Not available with in I2T loop. Reset bit back to 0 after ABIST has been run
0h = ABIST not Running
1h = ABIST for ADC Running
3ISNS_ABIST_RUNR/W0h Run the ABIST diaagnostics for the ISNS good signal and update the DIAG_RESULT register with the result. Not available when in I2T loop. Reset bit back to 0 after ABIST has been run
0h = ABIST not Running
1h = ABIST for ISNS Running
2RESERVEDR0h Reserved
1BG_ABIST_RUNR/W0h Run the ABIST diaagnostics for the Band Gap good signal and update the DIAG_RESULT register with the result. Reset bit back to 0 after ABIST has been run
0h = ABIST not Running
1h = ABIST for BG Running
0ADC_ENR/W0h Setting this bit to 1, enables the ADC function
0h = ADC function disabled
1h = ADC enabled

8.5.9 DEV_CONFIG Register (Offset = 9h) [Reset = 0000h]

DEV_CONFIG is shown in Table 8-15.

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Table 8-15 DEV_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR0h Reserved
6PWM_SHIFT_DISR/W0h Set this bit to 1 to disable the PWM delay between channels.
0h = PWM rising edges delayed by 100 us on the first rising edge
1h = PWM delay (offset) is disabled so rising edges are aligned
5RESERVEDR0h Reserved
4PARALLEL_12R/W0h Set this bit to 1 to signal that channels 1 and 2 (CH1 and CH2) are paralleled. Write to this bit is valid only when all SW_STATE Channel enable bits are 0 and not rewritten to 1 in the same frame.
0h = CH1 and CH2 are not paralleled together
1h = CH1 and CH2 are paralleled together
3WD_ENR/W0h The bit is set to enable the watchdog function. The watchdog is triggered if there is not a valid SPI command in the watchdog timeout window
0h = Watchdog is disabled
1h = Watchdog function is enabled
2-1WD_TOR/W0h Sets the timeout period for the SPI watchdog monitor. The watchdog timeout is triggered if there is not a valid SPI command in the watchdog timeout window
0h = Watchdog timeout 400 us
1h = Watchdog timeout is 400 ms
2h = Watchdog timeout is 800 ms
3h = Watchdog timeout is 1200 ms
0FLT_LTCH_DISR/W0h Set this bit to 1 to not latch the fault bits in the register and cleared on read.
0h = Fault bits in FAULT_TYPE_STAT register latched and cleared only on read
1h = Fault bits in FAULT_TYPE_STAT register not latched, cleared when the fault disappears

8.5.10 ADC_CONFIG Register (Offset = Ah) [Reset = 001Ah]

ADC_CONFIG is shown in Table 8-16.

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Table 8-16 ADC_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0h Reserved
4ADC_VSNS_DISR/W1h Set this bit to 1 to disable VOUT sense functionality, exclude VOUT conversion in the ADC conversion sequence.
0h = VOUTSNS ADC functionality enabled, include VOUT_SNS ADC conversion in the sequence
1h = VOUTSNS ADC functionality is disabled
3ADC_TSNS_DISR/W1h Set this bit to 1 to disable TEMP sense functionality, exclude TSNS conversion in the ADC conversion sequence.
0h = TSNS ADC functionality enabled, include TSNS ADC conversion in the sequence
1h = TSNS ADC functionality is disabled
2ADC_ISNS_DISR/W0h Set this bit to 1 to disable ISNS functionality, exclude ISNS conversion in the ADC conversion sequence.
0h = ISNS ADC functionality enabled, include ISNS ADC conversion in the sequence
1h = ISNS ADC functionality is disabled
1ADC_VBB_DISR/W1h Set this bit to 1 to disable VBB_SNS functionality, exclude supply voltage V_VBB conversion in the ADC conversion sequence.
0h = VBB_SNS ADC functionality is enabled, Include supply voltage V_VBB ADC conversion in the sequence
1h = VBB_SNS ADC functionality is disabled
0RESERVEDR0h Reserved

8.5.11 ADC_RESULT_VBB Register (Offset = Bh) [Reset = 0000h]

ADC_RESULT_VBB is shown in Table 8-17.

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Table 8-17 ADC_RESULT_VBB Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10VBB_RDYR0h Making sure the ADC conversion is new from the last time this was read
0h = VBB ADC Value not updated
1h = New VBB ADC Value Ready
9-0ADC_RESULT_VBBR0h ADC result (10-bits) from the conversion of the VBB voltage

8.5.12 FLT_STAT_CH1 Register (Offset = Dh) [Reset = 0000h]

FLT_STAT_CH1 is shown in Table 8-18.

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Table 8-18 FLT_STAT_CH1 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11LATCH_STAT_CH1R0h The bit is high if the channel has been latched off after a fault that shut down the channel. Clears when the channel is toggled back on
0h = CH1 is not latched off
1h = CH1 is currently latched off
10FLT_CH1R0h The bit is set if any type of real time fault (reverse current, thermal shutdown, open load (on/off-state) or short to supply) occurs in CH1
0h = No fault in CH1
1h = One or more fault has occurred in CH1
9SW_STATE_STAT_CH1R0h Current state of the channel no matter which mode the device is in as long as SPI is readable
0h = CH1 is OFF
1h = CH1 is ON
8RESERVEDR0h Reserved
7I2T_FLT_CH1R0h The bit is set if there is a fault from I2T setting (overcurrent). Only can go high if I2T_EN is high and an associated fault occurs on that channel. Cleared when FLT_STAT_CH1 register is read and fault condition does not exist anymore
0h = no I2T fault or I2T is not enabled
1h = I2T fault has occurred on CH1
6LPM_WAKE_CH1R0h This bit is set if this channel was the reason the device came out of LPM regardless of why
0h = The device was not in LPM or this channel was not the one that cause the device to come out of LPM
1h = This channel was the reason the device came out of LPM
5THERMAL_SD_CH1R0h The bit is set if the thermal shutdown has occurred at any time in CH1. The fault is latched and cleared when the FLT_STAT_CH1 register is read and channel temperature has fallen below the thermal shutdown reset threshold.
0h = No thermal shutdown fault in CH1
1h = Thermal shutdown has occurred in CH1
4ILIMIT_CH1R0h The bit is set if FET turn-off due to overcurrent has occurred at any time in CH1. The fault is latched and cleared when the FLT_STAT_CH1 register is read and fault condition does not exist anymore. Disabled if I2T mode is enabled
0h = No overcurrent protection fault in CH1
1h = FET turn-off due to overcurrent fault has occurred in CH1
3SHRT_VBB_CH1R0h The bit is set if short to VBB has occurred at any time in CH1. The fault is latched and cleared when the FLT_STAT_CH1 register is read and fault condition does not exist anymore. OL_SHRTVBB_DIFF_CH1 must have been enabled previously
0h = No Short to VBB fault in CH1 or short to VBB in OFF state not enabled
1h = Short to VBB Fault
2OL_OFF_CH1R0h The bit is set if the open load off state threshold been triggered. Only valid if OL_OFF_EN_CH1 is active. Device is pulled up with the threshold set by OL_PULLUP_STR
0h = No off state open load fault in CH1 or OL detection in OFF state not enabled
1h = Off State Open Load Fault
1OL_ON_CH1R0h Has the open load on state threshold been triggered? Only valid if OL_ON_EN_CH1 is active. Device is in high resistance mode
0h = No on state open load fault in CH1 or OL detection in OFF state not enabled
1h = On State Open Load Fault
0THERMAL_WRN_CH1R0h The bit is set if FET temperature is above the overtemperature warning threshold in CH1. The bit is cleared when over-temperature earning condition does not exist anymore.
0h = FET temperatire below over-temperature warning threshold in CH1
1h = FET temperatire above over-temperature warning threshold in CH1

8.5.13 PWM_CH1 Register (Offset = Eh) [Reset = 0000h]

PWM_CH1 is shown in Table 8-19.

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Table 8-19 PWM_CH1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11-9PWM_FREQ_CH1R/W0h Set the PWM frequency
0h = 0.8 Hz
1h = 3.4 Hz
2h = 13.8 Hz
3h = 111 Hz
4h = 221 Hz
5h = 443 Hz
6h = 885 Hz
7h = 1770 Hz
8-1PWM_DTY_CH1R/W0h 8 bit to set duty cycle for PWM operation of CH1. Each bit ~0.39% duty cycle, linearly up to 100% dutycycle.
0PWM_EN_CH1R/W0h Enable PWMing of the output if on cycle of PWM is >200us. If not return error in FLT_STAT_CH1 register. PWM mode cannot be enabled unless CAP_CHRGx [1:0] = 00
0h = Output follows SW_STATE behavior (ON/OFF)
1h = Output is PWMing according to duty cycle and frequency set if SW_STATE CH1 is ON

8.5.14 ILIM_CONFIG_CH1 Register (Offset = Fh) [Reset = 0088h]

ILIM_CONFIG_CH1 is shown in Table 8-20.

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Table 8-20 ILIM_CONFIG_CH1 Register Field Descriptions
BitFieldTypeResetDescription
15-14OCP_INRUSH_CH1R/W0h When CAP_CHRG=11, sets the overcurrent turn-off threshold during inrush phase and thus the peak current of the current pulse.
0h = Sets overcurrent turn-off and peak current to 47.5A
1h = Sets overcurrent turn-off and peak current to 55 A
Ah = Sets overcurrent turn-off and peak current to 62.5 A
Bh = Sets overcurrent turn-off and peak current to 70 A
13-12CAP_CHRG_CH1R/W0h Puts the part into the capacitive load driving mode. Turns on the INRUSH_LIMIT_CH1 bits to set the overcurrent protection or cap charging levels within the INRUSH_DURATION period and during that time there is no PWM or I2T
0h = No cap charging mode (immediate shutdown only)
1h = Cap charging mode dV/dt
2h = Cap charging mode current limit regulation mode.
3h = Cap charging mode - current pulse method
11I2T_EN_CH1R/W0h Enables the I2T functionality for Channel 1. I2T can be enabled before the channel is enabled or charges up, but the I2T calculation will start after the cap charge period ends If the cap charging mode is enabled (CAP_CHRG_CH1 [1:0] ne 00) .
0h = I2T functionality not enabled
1h = I2T functionality is enabled
10-8INRUSH_DURATION_CH1R/W0h Sets the delay period during with inrush current limit level applies.
0h = 0
1h = 2
2h = 4
3h = 6
4h = 10
5h = 20
6h = 50
7h = 100 ms
7-4INRUSH_LIMIT_CH1_OR_CAP_CHRG_DVDTR/W8h Overcurrent protection thresholds if CAP_CHRG_CH1 = 00. Becomes cap charging mode control bits when in cap charging mode. This means instead of having an overcurrent protection threshold setting for an inrush period, the bits are used to set the cap charging control bits setting either the dV/dt rate (CAP_CHRG_CH1 = 01), current limit (regulation) level (CAP_CHRG_CH1 = 10) or pulsed current mode parameters. (CAP_CHRG_CH1 = 11). When CAP_CHRG_CH1 = 00, then the same table as ILIMIT_SET_CH1 applies for overcurrent protection threshold during the INRUSH_DURATION. When CAP_CHRG_CH1 = 10, then the current limit threshold is below table with the value divided by 5. When CAP_CHRG_CH1 = 01, 4-bits will be used to set the dV/dt or voltage ramp rate per the table below. Only the specified bit settings are supported.
3h = 2.22 V/ms
5h = 1.0 V/ms
6h = 1.33 V/ms
7h = 1.66 V/ms
9h = 0.67 V/ms
Ah = 0.89 V/ms
Bh = 1.1 V/ms
Ch = 0.33 V/ms
Dh = 0.50 V/ms
3-0ILIMIT_SET_CH1R/W8h Setting the overcurrent protection threshold after the INRUSH_DURATION period.
0h = 10 A
1h = 12.5 A
2h = 15 A
3h = 17.5 A
4h = 20 A
5h = 22.5 A
6h = 25 A
7h = 32.5 A
8h = 40 A
9h = 47.5 A
Ah = 55 A
Bh = 62.5 A
Ch = 70 A Other settings are not supported.

8.5.15 DIAG_CONFIG_CH1 Register (Offset = 10h) [Reset = C002h]

DIAG_CONFIG_CH1 is shown in Table 8-21.

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Table 8-21 DIAG_CONFIG_CH1 Register Field Descriptions
BitFieldTypeResetDescription
15VSNS_DIS_CH1R/W1h Set this bit to 1 to disable the VSNS ADC functionality for this channel
0h = VSNS ADC functionality enabled
1h = VSNS ADC functionality is disabled
14TSNS_DIS_CH1R/W1h Set this bit to 1 to disable the ADC TSNS functionality for this channel
0h = TSNS ADC functionality enabled
1h = TSNS ADC functionality is disabled
13ISNS_DIS_CH1R/W0h Set this bit to 1 to disable ISNS ADC functionality for this channel
0h = ISNS ADC functionality enabled
1h = ISNS ADC functionality is disabled
12-11OL_ON_THLD_CH1R/W0h Sets the open load detection threshold in the on state. 2 bits to set the open load detection threshold, not implemented in current silicon revision
0h = TBD
1h = TBD
2h = TBD
3h = TBD
10ISNS_SCALE_CH1R/W0h Turns on 8x scaling of voltage input to the ADC to improve the current sense resolution
0h = ADC input voltage scale equals 1
1h = ADC input voltage scale equals 8
9OL_ON_EN_CH1R/W0h Turns on a more accurate open load detection in the on state with KSNS ratio scaled to lower value. This will set the FET into high Rdson mode therefore this cannot be enabled if there is an existing fault on the channel or the current is too high
0h = KSNS ratio and FET Rdson unchanged
1h = Enable Open Load Detection with a lower KSNS ratio and higher Rdson
8-7OL_SVBB_BLANK_CH1R/W0h Sets the blanking time for open load (ON-state and OFF-state) and the short_to_VBB faults before the fault is registered.
0h = Blanking time is 0.4 ms
1h = Blanking time is 1.0 ms
2h = Blanking time is 2.0 ms
3h = Blanking time is 4.0 ms
6-5OL_PU_STR_CH1R/W0h Sets the pullup current value (at the OUTx pins) by the off-state open load detection circuit.
0h = I_pu is 32 uA
1h = I_pu is 64 uA
2h = I_pu is 128 uA
3h = I_pu is 256 uA
4OL_OFF_EN_CH1R/W0h Turns on the pull up to see if there is an open load in the off state. Cannot bet set high if channel is on or fault exists
3SVBB_EN_CH1R/W0h Turns on the pull down to see if there is a short to VBB in the off state. Cannot bet set high if channel is on or fault exists
2LATCH_CH1R/W0h If fault occurs that channel shuts down, this bit sets if the channel auto retries or latches off
0h = Auto retry after tRETRY and Thys
1h = latch off until SW_STATE register is written to again
1-0SLRT_CH1R/W2h Slew Rate set for ouput of CH1. 4 different slew rate values for adjustable slew rate per electrical characteristics table

8.5.16 ADC_RESULT_CH1_I Register (Offset = 11h) [Reset = 0000h]

ADC_RESULT_CH1_I is shown in Table 8-22.

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Table 8-22 ADC_RESULT_CH1_I Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10ISNS_RDY_CH1R0h Making sure the ADC conversion is new from the last time this was read
9-0ADC_RESULT_CH1_IR0h ADC result (10-bits) from the conversion of the current in CH1

8.5.17 ADC_RESULT_CH1_T Register (Offset = 12h) [Reset = 0000h]

ADC_RESULT_CH1_T is shown in Table 8-23.

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Table 8-23 ADC_RESULT_CH1_T Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10TSNS_RDY_CH1R0h Making sure the ADC conversion is new from the last time this was read
9-0ADC_RESULT_CH1_TR0h ADC result (10-bits) from the conversion of the temperature in CH1

8.5.18 ADC_RESULT_CH1_V Register (Offset = 13h) [Reset = 0000h]

ADC_RESULT_CH1_V is shown in Table 8-24.

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Table 8-24 ADC_RESULT_CH1_V Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10VSNS_RDY_CH1R0h Making sure the ADC conversion is new from the last time this was read
9-0ADC_RESULT_CH1_VR0h ADC result (10-bits) from the conversion of the output voltage in CH1

8.5.19 I2T_CONFIG_CH1 Register (Offset = 14h) [Reset = 0000h]

I2T_CONFIG_CH1 is shown in Table 8-25.

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Table 8-25 I2T_CONFIG_CH1 Register Field Descriptions
BitFieldTypeResetDescription
15-14TCLDN_CH1R/W0h 2bits to Set cool down time for I2T functionality for Channel 1 (time to retry after I2T shutdown.
0h = Latch mode (or no retry)
1h = 0.8 s
2h = 2.0 s
3h = 4.0 s
13-11RESERVEDR0h Reserved
10-9SWCL_DLY_TMR_CH1R/W0h 2-bits to set delayed turn-off timer for Channel 1. Sets the time after which the channel shuts down when the current exceeds ISWCL.
0h = 0.2 ms
1h = 0.4 ms
2h = 1.0 ms
3h = 2.0 ms
8-7ISWCL_CH1R/W0h 2bits to set delayed turn-off current threshold value for I2T functionality for Channel 1. The threshold should be set below the maximum current sensed with the sense resistor chosen. The current threshold assumes a sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 19.55
1h = 17.6
2h = 16.05
3h = 13.3
6-3I2T_TRIP_CH1R/W0h 4bits to Set Trip value for I2T functionality for Channel 1. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs and the threshold changes by the square of the current.
0h = 8.8 A2s
1h = 13.1 A2s
2h = 26.3 A2s
3h = 39.4 A2s
4h = 52.5 A2s
5h = 65.6 A2s
6h = 78.8 A2s
7h = 91.9 A2s
8h = 109.4 A2s
9h = 126.9 A2s
Ah = 144.4 A2s
Bh = 166.3 A2s
Ch = 192.5 A2s
Dh = 218.8 A2s
Eh = 262.5 A2s
Fh = 350 A2s
2-0NOM_CUR_CH1R/W0h 3 bits to set the nomial current value of Channel 1. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 4.0 A
1h = 5.0 A
2h = 5.7 A
3h = 6.5 A
4h = 7.5 A
5h = 9.0 A
6h = 12.0 A
7h = 15.0 A

8.5.20 FLT_STAT_CH2 Register (Offset = 15h) [Reset = 0000h]

FLT_STAT_CH2 is shown in Table 8-26.

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Table 8-26 FLT_STAT_CH2 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11LATCH_STAT_CH2R0h The bit is high if the channel has been latched off after a fault that shut down the channel. Clears when the channel is toggled back on
0h = CH2 is not latched off
1h = CH2 is currently latched off
10FLT_CH2R0h The bit is set if any type of real time fault (reverse current, thermal shutdown, open load (on/off-state) or short to supply) occurs in CH2
0h = No fault in CH2
1h = One or more fault has occurred in CH2
9SW_STATE_STAT_CH2R0h Current state of the channel no matter which mode the device is in as long as SPI is readable
0h = CH2 is OFF
1h = CH2 is ON
8RESERVEDR0h Reserved
7I2T_FLT_CH2R0h The bit is set if there is a fault from I2T setting (overcurrent). Only can go high if I2T_EN is high and an associated fault occurs on that channel. Cleared when FLT_STAT_CH2 register is read and fault condition does not exist anymore
0h = no I2T fault or I2T is not enabled
1h = I2T fault has occurred on CH2
6LPM_WAKE_CH2R0h This bit is set if this channel was the reason the device came out of LPM regardless of why
0h = The device was not in LPM or this channel was not the one that cause the device to come out of LPM
1h = This channel was the reason the device came out of LPM
5THERMAL_SD_CH2R0h The bit is set if the thermal shutdown has occurred at any time in CH2. The fault is latched and cleared when the FLT_STAT_CH2 register is read and channel temperature has fallen below the thermal shutdown reset threshold.
0h = No thermal shutdown fault in CH2
1h = Thermal shutdown has occurred in CH2
4ILIMIT_CH2R0h The bit is set if FET turn-off due to overcurrent has occurred at any time in CH2. The fault is latched and cleared when the FLT_STAT_CH2 register is read and fault condition does not exist anymore.
0h = No overcurrent rprotection fault in CH2
1h = FET turn-off due to overcurrent fault has occurred in CH2
3SHRT_VBB_CH2R0h The bit is set if short to VBB has occurred at any time in CH2. The fault is latched and cleared when the FLT_STAT_CH2 register is read and fault condition does not exist anymore. OL_SHRTVBB_DIFF_CH2 must have been enabled previously
0h = No Short to VBB fault in CH2 or short to VBB in OFF state not enabled
1h = Short to VBB Fault
2OL_OFF_CH2R0h Has the open load off state threshold been triggered? Only valid if OL_OFF_EN_CH2 is active. Device is pulled up with the threshold set by OL_PULLUP_STR
0h = No off state open load fault in CH2 or OL detection in OFF state not enabled
1h = Off State Open Load Fault
1OL_ON_CH2R0h Has the open load on state threshold been triggered? Only valid if OL_ON_EN_CH2 is active. Device is in high resistance mode
0h = No on state open load fault in CH2 or OL detection in OFF state not enabled
1h = On State Open Load Fault
0THERMAL_WRN_CH2R0h The bit is set if FET temperature is above the overtemperature warning threshold in CH2. The bit is cleared when over-temperature earning condition does not exist anymore.
0h = FET temperatire below over-temperature warning threshold in CH2
1h = FET temperatire above over-temperature warning threshold in CH2

8.5.21 PWM_CH2 Register (Offset = 16h) [Reset = 0000h]

PWM_CH2 is shown in Table 8-27.

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Table 8-27 PWM_CH2 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11-9PWM_FREQ_CH2R/W0h Set the PWM frequency
0h = 0.8 Hz
1h = 3.4 Hz
2h = 13.8 Hz
3h = 111 Hz
4h = 221 Hz
5h = 443 Hz
6h = 885 Hz
7h = 1770 Hz
8-1PWM_DTY_CH2R/W0h 8 bit to set duty cycle for PWM operation of CH2. Each bit ~0.39% duty cycle
0PWM_EN_CH2R/W0h Enable PWMing of the output if on cycle of PWM is >200us. If not return error in FLT_STAT_CH2 register. PWM mode cannot be enabled unless CAP_CHRGx [1:0] = 00
0h = Output follows SW_STATE behavior (ON/OFF)
1h = Output is PWMing according to duty cycle and frequency set if SW_STATE CH2 is ON

8.5.22 ILIM_CONFIG_CH2 Register (Offset = 17h) [Reset = 0088h]

ILIM_CONFIG_CH2 is shown in Table 8-28.

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Table 8-28 ILIM_CONFIG_CH2 Register Field Descriptions
BitFieldTypeResetDescription
15-14OCP_INRUSH_CH2R/W0h When CAP_CHRG=11, sets the overcurrent turn-off threshold during inrush phase and thus the peak current of the current pulse.
0h = Sets overcurrent turn-off and peak current to 47.5A
1h = Sets overcurrent turn-off and peak current to 55 A
Ah = Sets overcurrent turn-off and peak current to 62.5 A
Bh = Sets overcurrent turn-off and peak current to 70 A
13-12CAP_CHRG_CH2R/W0h Puts the part into the capacitive load driving mode. Turns on the INRUSH_LIMIT_CH2 bits to set the overcurrent protection or cap charging levels within the INRUSH_DURATION period and during that time there is no PWM or I2T
0h = No cap charging mode (immediate shutdown only)
1h = Cap charging mode dV/dt
2h = Cap charging mode current limit regulation mode.
3h = Cap charging mode - current pulse method
11I2T_EN_CH2R/W0h Enables the I2T functionality for Channel 2. I2T can be enabled before the channel is enabled or charges up, but the I2T calculation will start after the cap charge period ends If the cap charging mode is enabled (CAP_CHRG_CH2 [1:0] ne 00) .
10-8INRUSH_DURATION_CH2R/W0h Sets the delay period during with inrush current limit level applies. See table of delay settings in the datasheet.
0h = 0
1h = 2
2h = 4
3h = 6
4h = 10
5h = 20
6h = 50
7h = 100 ms
7-4INRUSH_LIMIT_CH2_OR_CAP_CHRG_DVDTR/W8h Overcurrent protection thresholds if CAP_CHRG_CH1 = 00. Becomes cap charging mode control bits when in cap charging mode. This means instead of having an overcurrent protection threshold setting for an inrush period, the bits are used to set the cap charging control bits setting either the dV/dt rate (CAP_CHRG_CH1 = 01), current limit (regulation) level (CAP_CHRG_CH1 = 10) or pulsed current mode parameters. (CAP_CHRG_CH1 = 11). When CAP_CHRG_CH1 = 00, then the same table as ILIMIT_SET_CH1 applies for overcurrent protection threshold during the INRUSH_DURATION. When CAP_CHRG_CH1 = 10, then the current limit threshold is below table with the value divided by 5. When CAP_CHRG_CH1 = 01, 4-bits will be used to set the dV/dt or voltage ramp rate per the table below. Only the specified bit settings are supported.
3h = 2.22 V/ms
5h = 1.0 V/ms
6h = 1.33 V/ms
7h = 1.66 V/ms
9h = 0.67 V/ms
Ah = 0.89 V/ms
Bh = 1.1 V/ms
Ch = 0.33 V/ms
Dh = 0.50 V/ms
3-0ILIMIT_SET_CH2R/W8h Setting the overcurrent protection threshold after the INRUSH_DURATION period.
0h = 10 A
1h = 12.5 A
2h = 15 A
3h = 17.5 A
4h = 20 A
5h = 22.5 A
6h = 25 A
7h = 32.5 A
8h = 40 A
9h = 47.5 A
Ah = 55 A
Bh = 62.5 A
Ch = 70 A Other settings are not supported.

8.5.23 DIAG_CONFIG_CH2 Register (Offset = 18h) [Reset = C002h]

DIAG_CONFIG_CH2 is shown in Table 8-29.

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Table 8-29 DIAG_CONFIG_CH2 Register Field Descriptions
BitFieldTypeResetDescription
15VSNS_DIS_CH2R/W1h Set this bit to 1 to disable the VSNS ADC functionality for this channel
0h = VSNS ADC functionality enabled
1h = VSNS ADC functionality is disabled
14TSNS_DIS_CH2R/W1h Set this bit to 1 to disable the ADC TSNS functionality for this channel
0h = TSNS ADC functionality enabled
1h = TSNS ADC functionality is disabled
13ISNS_DIS_CH2R/W0h Set this bit to 1 to disable ISNS ADC functionality for this channel
0h = ISNS ADC functionality enabled
1h = ISNS ADC functionality is disabled
12-11OL_ON_THLD_CH2R/W0h Sets the open load detection threshold in the on state. 2 bits to set the open load detection threshold, not implemented in current silicon revision
0h = TBD
1h = TBD
2h = TBD
3h = TBD
10ISNS_SCALE_CH2R/W0h Turns on 8x scaling of voltage input to the ADC to improve the current sense resolution
0h = ADC input voltage scale equals 1
1h = ADC input voltage scale equals 8
9OL_ON_EN_CH2R/W0h Turns on a more accurate open load detection in the on state with KSNS ratio scaled to lower value. This will set the FET into high Rdson mode therefore this cannot be enabled if there is an existing fault on the channel or the current is too high
0h = KSNS ratio and FET Rdson unchanged
1h = Enable more accurate Open Load Detection with a lower KSNS ratio and higher Rdson
8-7OL_SVBB_BLANK_CH2R/W0h Sets the blanking time for open load (ON-state and OFF-state) and the short_to_VBB faults before the fault is registered.
0h = Blanking time is 0.4 ms
1h = Blanking time is 1.0 ms
2h = Blanking time is 2.0 ms
3h = Blanking time is 4.0 ms
6-5OL_PU_STR_CH2R/W0h Sets the pullup current value (at the OUTx pins) by the off-state open load detection circuit.
0h = I_pu is 32 uA
1h = I_pu is 64 uA
2h = I_pu is 128 uA
3h = I_pu is 256 uA
4OL_OFF_EN_CH2R/W0h Turns on the pull up to see if there is an open load in the off state. Cannot bet set high if channel is on or fault exists
3SVBB_EN_CH2R/W0h Turns on the pull down to see if there is a short to VBB in the off state. Cannot bet set high if channel is on or fault exists
2LATCH_CH2R/W0h If fault occurs that channel shuts down, this bit sets if the channel auto retries or latches off
0h = Auto retry after tRETRY and Thys
1h = latch off until SW_STATE register is written to again
1-0SLRT_CH2R/W2h Slew Rate set for ouput of CH1. 4 different slew rate values for adjustable slew rate per electrical characteristics table

8.5.24 ADC_RESULT_CH2_I Register (Offset = 19h) [Reset = 0000h]

ADC_RESULT_CH2_I is shown in Table 8-30.

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Table 8-30 ADC_RESULT_CH2_I Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10ISNS_RDY_CH2R0h Making sure the ADC conversion is new from the last time this was read
9-0ADC_RESULT_CH2_IR0h ADC result (10-bits) from the conversion of the current in CH2

8.5.25 ADC_RESULT_CH2_T Register (Offset = 1Ah) [Reset = 0000h]

ADC_RESULT_CH2_T is shown in Table 8-31.

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Table 8-31 ADC_RESULT_CH2_T Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10TSNS_RDY_CH2R0h Making sure the ADC conversion is new from the last time this was read
9-0ADC_RESULT_CH2_TR0h ADC result (10-bits) from the conversion of the temperature in CH2

8.5.26 ADC_RESULT_CH2_V Register (Offset = 1Bh) [Reset = 0000h]

ADC_RESULT_CH2_V is shown in Table 8-32.

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Table 8-32 ADC_RESULT_CH2_V Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10VSNS_RDY_CH2R0h Making sure the ADC conversion is new from the last time this was read
9-0ADC_RESULT_CH2_VR0h ADC result (10-bits) from the conversion of the output voltage in CH2

8.5.27 I2T_CONFIG_CH2 Register (Offset = 1Ch) [Reset = 0000h]

I2T_CONFIG_CH2 is shown in Table 8-33.

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Table 8-33 I2T_CONFIG_CH2 Register Field Descriptions
BitFieldTypeResetDescription
15-14TCLDN_CH2R/W0h 2bits to Set cool down time for I2T functionality for Channel 2 (time to retry after I2T shutdown.
0h = Latch mode (or no retry)
1h = 0.8 s
2h = 2.0 s
3h = 4.0 s
13-11RESERVEDR0h Reserved
10-9SWCL_DLY_TMR_CH2R/W0h 2-bits to set delayed turn-off timer for Channel 2. Sets the time after which the channel shuts down when the current exceeds ISWCL.
0h = 0.2 ms
1h = 0.4 ms
2h = 1.0 ms
3h = 2.0 ms
8-7ISWCL_CH2R/W0h 2-bits to set delayed turn-off current threshold value for I2T functionality for Channel 2. The threshold should be set below the maximum current sensed with the sense resistor chosen. The current threshold assumes a sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 19.55
1h = 17.6
2h = 16.05
3h = 13.3
6-3I2T_TRIP_CH2R/W0h 4-bits to Set Trip value for I2T functionality for Channel 1. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs and the threshold changes by the square of the current.
0h = 8.8 A2s
1h = 13.1 A2s
2h = 26.3 A2s
3h = 39.4 A2s
4h = 52.5 A2s
5h = 65.6 A2s
6h = 78.8 A2s
7h = 91.9 A2s
8h = 109.4 A2s
9h = 126.9 A2s
Ah = 144.4 A2s
Bh = 166.3 A2s
Ch = 192.5 A2s
Dh = 218.8 A2s
Eh = 262.5 A2s
Fh = 350 A2s
2-0NOM_CUR_CH2R/W0h 3 bits to set the nomial current value of Channel 2. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 4.0 A
1h = 5.0 A
2h = 5.7 A
3h = 6.5 A
4h = 7.5 A
5h = 9.0 A
6h = 12.0 A
7h = 15.0 A