SLVSGY2 October   2023 TPS2HCS10-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Programmable Fuse Protection
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Overcurrent Protection And Capacitive Load Charging
        4. 8.3.1.4 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Channel Output (FET) Enabled
          2. 8.3.2.1.2 Detection With Channel Output Disabled
        2. 8.3.2.2 Digital Current Sense Output
          1. 8.3.2.2.1 RSNS Value and Accuracy / Resolution of Current Measurement
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Output Voltage and FET Temperature Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 SLEEP
      3. 8.4.3 CONFIG/ACTIVE
      4. 8.4.4 Battery Supply Input (VBB) Under-voltage
      5. 8.4.5 LOW POWER MODE (LPM) State
      6. 8.4.6 LIMP HOME state
      7. 8.4.7 SPI Mode Operation
    5. 8.5 TPS2HC10S Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.4 Battery Supply Input (VBB) Under-voltage

The device includes a battery supply (VBB) under-voltage monitoring. Some of the internal reference and regulators and the output FETs are turned OFF when the VBB supply falls below the VBBUVLOF threshold. When the input VBB supply is lost, the device relies on the low voltage supply input to keep the digital functions and registers alive. The SPI communication is also available as long as VDD input is supplied. The VBB UVLO error fault bits can be read over SPI from the CH_FLT_TYPE_FAULT_GLOBAL_TYPE register (VBB_UVLO bit). The following table indicates the device operation under a loss of supply condition.

Table 8-2 Device operation under supply loss condition
VDD < VDD_UVLO VDD > VDD_UVLO
VBB < VBB_UVLO
  • Channels are OFF
  • Registers are reset and digital core OFF
  • SPI communication not possible
  • Channels are OFF
  • Registers are maintained and digital core is ON
  • SPI communication possible
VBB > VBB_UVLO
  • Device is in LIMP HOME mode, channels set by LIMP_HOME mode programming
  • Registers are maintained and digital core is ON
  • SPI communication not possible
  • Channels are controlled by SPI register writes
  • Registers are maintained and digital core is ON
  • SPI communication possible

The register information may be lost when both the VBB and VDD supplies are below the POR and UVLO conditions respectively. The device is able to indicate with a register read of the POR bit in the CH_FLT_TYPE_FAULT_GLOBAL_TYPE register that a reset of the digital has occurred. This will ensure that the SPI master can identify that the register contents are all lost and the configuration registers needs to be rewritten. It is recommended that the bit be read if any under-voltage fault is detected