SLVSGY2 October   2023 TPS2HCS10-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Programmable Fuse Protection
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Overcurrent Protection And Capacitive Load Charging
        4. 8.3.1.4 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Channel Output (FET) Enabled
          2. 8.3.2.1.2 Detection With Channel Output Disabled
        2. 8.3.2.2 Digital Current Sense Output
          1. 8.3.2.2.1 RSNS Value and Accuracy / Resolution of Current Measurement
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Output Voltage and FET Temperature Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 SLEEP
      3. 8.4.3 CONFIG/ACTIVE
      4. 8.4.4 Battery Supply Input (VBB) Under-voltage
      5. 8.4.5 LOW POWER MODE (LPM) State
      6. 8.4.6 LIMP HOME state
      7. 8.4.7 SPI Mode Operation
    5. 8.5 TPS2HC10S Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VBB = 6 V to 18 V, VDD = 3.0 V to 5.5 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENT
VClamp VDS clamp voltage  FET current = 10 mA  VBB > 28 V TJ = 25°C to 150°C 35 40 45 V
VClamp VDS clamp voltage  FET current = 10 mA  12 V < VBB < 28 V TJ = –40°C to 150°C 30 34 38 V
VClamp VDS clamp voltage  FET current = 10 mA VBB = 3 V TJ = –40°C to 150°C 27.5 36.5 V
VVBB_UVLOR VBB undervoltage lockout rising Measured with respect to the GND pin of the device, FETs can turn-on above this level, full switch functionality and OCP and TSD protection. Diagnostics only at > 6 V Measured with respect to the GND pin of the device, FETs can turn-on above this level, full switch functionality and OCP and TSD protection. Diagnostics only at > 6 V 3.0 3.5 4.0 V
VVBB_UVLOF VBB undervoltage lockout falling Measured with respect to the GND pin of the device, FETs  turn-off below this level. Measured with respect to the GND pin of the device, FETs  turn-off below this level. 2.6 2.8 3.0 V
VBB_UV_WRN_R VBB voltage UV_WRN bit is set (rising threshold) Measured with respect to the GND pin of the device. VBB undervoltage at which diagnostics is turned ON. 4.9 V
VBB_UV_WRN_F VBB undervoltage at which diagnostics is turned OFF Measured with respect to the GND pin of the device. VBB undervoltage at which diagnostics are no longer available (turned OFF). Overcurrent and thermal protection is available till VBB_UVLO 4.5 V
VVDD_UVLOF VVDD  undervoltage lockout falling SPI communication is lost 1.95 2.07 V
VVDD_UVLOR VVDD undervoltage lockout rising Measured with respect to the GND pin of the device 2.02 2.2 V
VVDD_UVLOH VVDD undervoltage lockout hysteresis VUVLOR – VUVLOF 0.09 V
ILNOM Continuous load current, per channel All channels enabled, TAMB = 85°C 7 A
One channel enabled, TAMB = 85°C 12 A
ISLEEP,VBB Sleep current (total device leakage including all MOSFET channels) VBB ≤ 18 V, device in SLEEP mode, VOUT = 0 V TJ = 25°C
 		 0.3 µA
ISLEEP,VBB Sleep current (total device leakage including all MOSFET channels) VBB ≤ 18 V, device in SLEEP mode, VOUT = 0 V TJ = 85°C
 		 1.8 µA
IOUT(OFF) Output leakage current (per channel) from the FET, ACTIVE mode VBB ≤ 18 V, VOUT = 0
FET off, ACTIVE mode		 TJ = –40 to 125°C 12 µA
IDD Active State VDD quiescent current, SCLK off, ACTIVE state,  6 V < VBB ≤ 18 V, VDD = 5.5 V 1.5 mA
IDD Active State VDD quiescent current, SCLK off, ACTIVE state 6 V < VBB ≤ 18 V, VDD = 3.0 V 60 µA
IDDQ Active State VDD quiescent current, SCLK ON, 10 MHz, ACTIVE state 6 V < VBB ≤ 18 V, VDD = 5.5 V 2 mA
VBB IQ VBB quiescent current, SCLK off, all diagnostics disabled,(OL_OFF, OL_ON, SHRT_VS, ISNS, ADC)  VBB ≤ 18 V, VDD = 5.5 V
All channels enabled, IOUTx = 0 A		 2.35 2.75 mA
VBB IQ VBB quiescent current, SCLK off, all diagnostics disabled, (OL_OFF, OL_ON, SHRT_VS, ISNS, ADC)  VBB ≤ 18 V, VDD = 3.0 V
All channels enabled, IOUTx = 0 A		 3.6 4.5 mA
VBB IQ VBB quiescent current, SCLK off, all diagnostics (ISNS, ADC) enabled VBB ≤ 18 V, VDD = 3.0 V
All channels enabled, IOUTx = 0 A		 4.9 6 mA
RON CHARACTERISTICS
RON On-resistance
(Includes MOSFET and package)		 6 V ≤ VBB ≤ 28 V, IOUTx = 1 A TJ = 25°C 11.3 mΩ
RON On-resistance
(Includes MOSFET and package)		 6 V ≤ VBB ≤ 28 V, IOUTx = 1 A TJ = 150°C 22 mΩ
RON(REV) On-resistance during reverse polarity –18 V ≤ VBB ≤ –7 V TJ = 25°C 10 mΩ
TJ = 150°C 25 mΩ
CURRENT SENSE CHARACTERISTICS
KSNS Current sense ratio
IOUTx / ISNS		 IOUT = 1.0 A, OL_ON_EN_CHx = 0 IOUT = 1.0 A, OL_ON_EN_CHx = 0 5000
KSNS Current sense ratio
IOUTx / ISNS		 IOUT = 50 mA, OL_ON_EN_CHx = 1 IOUT = 50 mA, OL_ON_EN_CHx = 1 1200
ISNSI   Current sense current Channel current sense diagnostic ADC enabled, OL_ON_EN_CHx = 0 IOUT = 10 A (±4% error) 1.92 2.00 2.08 mA
ISNSI   Current sense current Channel current sense diagnostic ADC enabled, OL_ON_EN_CHx = 0 IOUT = 2 A (±4% error) 0.385 0.40 0.41 mA
ISNSI   Current sense current Channel current sense diagnostic ADC enabled, OL_ON_EN_CHx = 0 IOUT = 500 mA (±6% error) 0.096 0.10 0.106 mA
ISNSI   Current sense current Channel current sense diagnostic ADC enabled, OL_ON_EN_CHx = 1 IOUT = 25 mA (15 % error) 0.018 0.021 0.024 mA
ADC CHARACTERISTICS
VADCEFfHI ADC reference voltage 2.76 2.8 2.84 V
Isample Current sense sampling time Including mux timing and ADC conversion time 50 µs
IADC ADC current consumption 0.5  mA
SNS CHARACTERISTICS
ADC VOUTSNS_CHx ADC VOUTSNS output code VOUT_CHx = 13.5 V Includes buffer gain 459
OVERCURRENT PROTECTION CHARCTERISTICS
IOCth Overcurrent protection threshold, immediate shutdown mode TJ = –40°C to 125°C IOC setting = 62.5 A, VBB = 18 V  dI/dt = 2 A / µs 65 A
ICL_ENPS Peak current enabling into permanent short, immediate shutdown TJ = –40°C to 125°C OCP setting = 62.5 A, Test setup per AEC Q100-12 70 A
CAP CHRG CURRENT LIMITATION 
ICL_Reg Regulation mode current TJ = –40°C to 125°C  dI/dt  < 0.01 A/ms SPI Setting (ILIM_CHx_SET) of 10 A, IILIM = 2 A  1.70 2.15 2.5 A
ICL_Reg Regulation mode current TJ = –40°C to 125°C  dI/dt  < 0.01 A/ms SPI Setting (ILIM_CHx_SET) of 20 A, IILIM = 4 A  3.35 3.8 4.55 A
CAPACITIVE CHARGING
TDELAY_RANGE Range of Tdelay settings SPI settting, Pulsed current mode 1 100 ms
dV_dtRANGE Range of dV/dt during Tdelay SPI settting, dV/dt mode VBB = 16V,  Capacitance = 1 mF   0.33 1.6 V/ms
FAULT CHARACTERISTICS
IOL_OFF Off state open-load (OL) detection internal pull-up current Switch disabled, OL_OFF_EN_CHx = enabled  OL_PULLUP_STR=00 23 25 28 µA
OL_PULLUP_STR=01 52 57 63 µA
OL_PULLUP_STR=10 112 121 130 µA
OL_PULLUP_STR=11 235 256 265 µA
RSHRT_VBB Off state short to VBB detection pulldown resistance Channel disabled, off-state short_VBB diagnostics enabled 6 7.5 9 kΩ
VOL_OFF_TH Off state Open-load (OL) detection voltage Channel Disabled, off-state open load diagnostics enabled, VOUTx 1.9 2.5 2.95 V
TABS Thermal shutdown 155 180 205 °C
TOTW Thermal shutdown warning 130 150 170 °C
TREL Relative thermal shutdown temperature 60 °C
THYS Thermal shutdown hysteresis 20 25 30 °C
PWM CHARACTERISTICS
PWMFREQ PWM Frequency PWM_EN = 1 PWM_FREQ_CHx = 000 0.80 0.86 0.93 Hz
PWMFREQ PWM Frequency PWM_EN = 1 PWM_FREQ_CHx = 111 1637 1770 1903 Hz
LOW POWER MODE CHARACTERISTICS
RDSON RDSON Low Power Mode (LPM) TJ = –40°C to 125°C TJ = –40°C to 125°C 60 mΩ
ILOADEXIT Load current when the channel exits LPM Exit Threshold Setting = 00 (600 mA) Current ramp at 1 mA/µs 525 600 675 mA
IVDDLPM IVDD in LPM mode both channels ON  Iout = 0 VDD = 5.0 V TJ = –40°C to 85°C 14 µA
IVBBLPM IVBB per channel, both channels OFF, Iout = 0 VDD = 5.0 V TJ = –40°C to 85°C 2.5 µA
IVBBLPM IVBB per channel, one channel ON, Iout = 0 VDD = 5.0 V TJ = –40°C to 85°C 3.6 µA
IVBBLPM IVBB per channel, both channels ON, Iout = 0 VDD = 5.0 V TJ = –40°C to 85°C 4.5 µA
DIGITAL INPUT PIN CHARACTERISTIC
VIH, DIG Digital pin Input voltage high-level 3.0 V ≤ VDD ≤ 5.5 V 0.7 × VVDD V
VIL, DIG Digital pin Input voltage high-level 3.0 V ≤ VDD ≤ 5.5 V 0.3 × VVDD V
RDIGx Internal pulldown resistor 0.7 1.0 1.8 MΩ
IIH, DIG Input current high-level VDIG = 5 V 5 µA
DIGITAL OUTPUT PIN CHARACTERISTICS
VOH_SDO Output logic high voltage drop SDO pin current = 2 mA 0.2 V
VOL_FLT Output logic high voltage drop FLT pin current = 4mA 0.5 V