SLVSGY2 October   2023 TPS2HCS10-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Programmable Fuse Protection
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Overcurrent Protection And Capacitive Load Charging
        4. 8.3.1.4 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Channel Output (FET) Enabled
          2. 8.3.2.1.2 Detection With Channel Output Disabled
        2. 8.3.2.2 Digital Current Sense Output
          1. 8.3.2.2.1 RSNS Value and Accuracy / Resolution of Current Measurement
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Output Voltage and FET Temperature Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 SLEEP
      3. 8.4.3 CONFIG/ACTIVE
      4. 8.4.4 Battery Supply Input (VBB) Under-voltage
      5. 8.4.5 LOW POWER MODE (LPM) State
      6. 8.4.6 LIMP HOME state
      7. 8.4.7 SPI Mode Operation
    5. 8.5 TPS2HC10S Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

LIMP HOME state

LIMP HOME state is intended to place the outputs in the desired safe state when there is a failure of SPI communication or VDD supply. When the ECU detects a system-level fault, the system controller raises the LHI pin high to signal to the device the need to go into the LIMP HOME state. Also, if the device detects a SPI watch dog timeout error and thus an SPI communication error, the device goes to the LIMP HOME state. In both cases, the output state is as specified in the CHx_LH_IN bits of the DEVICE_STAT register.

The register values are retained in the LIMP HOME state, which means that the appropriate overcurrent protection threshold values, duration and retry behavior are all set with the outputs corresponding to the state based on the CHx_LH_IN bits. Additionally, the "LIMPHOME_STAT” bit in the CH_FLT_TYPE_FAULT_GLOBAL_TYPE register is set which lets the MCU or controller know that the device is in the LIMP HOME state. The MCU cannot write to any of the registers until the device is out of the LIMP HOME state.

Transitioning out of the LIMP HOME state

Device transitions out of the LIMP HOME state when the LHI pin goes low and then SPI writes a 1 to the LIMPHOME_STAT bit in the CH_FLT_TYPE_FAULT_GLOBAL_TYPE register. The register settings are reatined while in LIMP HOME state and the device transitions back into normal operation in the ACTIVE state

LIMP HOME state exceptions

  • The device can receive an LHI signal during cap charging or inrush duration. If the desired state is ON, the device continues cap charging per programmed register values. If the desired state is OFF, then the channel is turned off.

DI Pin Functionality

The DI pin determines the output state when the device goes into LIMP HOME state, if the CHx_LH_IN bits are set to 00 in the DEVICE_STAT register.

  • If DI is set HI, then CH1 = ON and CH2 = ON when in the LIMP HOME state
  • If DI is set LOW, then CH1 = OFF and CH2 = OFF when in the LIMP HOME state