SLUSF07 December   2024 TPS4813-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low-Power Bypass FET (G2 Drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET's (G1 Drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 State Transition Timing Diagram
      3. 7.4.3 Power Down
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 Low Power Mode
      6. 7.4.6 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application 1: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 12 V, V(BST – SRC) = 11 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VS Operating input voltage 3.5 95 V
V(S_PORR) Input supply POR threshold, rising 1.86 2.55 3.29 V
V(S_PORF) Input supply POR threshold, falling 1.73 2.36 3.02 V
I(Q) Total System Quiescent current, I(GND) in Active mode V(EN/UVLO) = V(LPM) = 2 V 43 55 µA
Total System Quiescent current, I(GND) in low power mode V(EN/UVLO) = 2 V, V(LPM) = 0 V 35 44 µA
  V(EN/UVLO) = 2 V, V(LPM) = 0 V, –40°C ≤ TJ ≤ +85°C 43 µA
I(SHDN) SHDN current, I(GND) V(EN/UVLO) = 0 V, V(SRC) = 0 V 1 3.3 µA
I(REV) I(VS) leakage current during Reverse Polarity  V(VS) = – 40 V 11 13 23 µA
ENABLE, UNDERVOLTAGE LOCKOUT (EN/UVLO), SHORT CIRCUIT COMPARATOR TEST (SCP_TEST) INPUT
V(UVLOR) UVLO threshold voltage, rising 1.176 1.23 1.287 V
V(UVLOF) UVLO threshold voltage, falling 1.06 1.13 1.184 V
V(ENR) Enable threshold voltage for low Iq shutdown, rising 1 V
V(ENF) Enable threshold voltage for low Iq shutdown, falling 0.3 V
I(EN/UVLO) Enable input leakage current V(EN/UVLO)  = 12 V 180 309 nA
V(SCP_TEST_H) SCP test mode rising threshold 2 V
V(SCP_TEST_L) SCP test mode falling threshold 0.8 V
I(SCP_TEST) SCP_TEST input leakage current 90 700 nA
CHARGE PUMP (BST–SRC)
I(BST) Charge Pump Supply current V(BST – SRC)  = 10 V, V(EN/UVLO) =  2 V 196 345 484 µA
V(BST_UVLOR) V(BST – SRC) UVLO voltage threshold, rising V(EN/UVLO) = 2 V 8.1 9 9.9 V
V(BST_UVLOF) V(BST – SRC) UVLO voltage threshold, falling V(EN/UVLO) = 2 V 7.3 8.2 8.9 V
V(BST–SRC_ON) Charge Pump Turn ON voltage V(EN/UVLO) = 2 V 9.3 10.3 11.4 V
V(BST–SRC_OFF) Charge Pump Turn OFF voltage V(EN/UVLO) = 2 V 10.4 11.6 12.8 V
V(BST–SRC) Charge Pump Voltage at V(VS) = 3.5 V V(EN/UVLO) = 2 V 9.1 10.5 11.62 V
V(G1_GOOD) G1 Good rising threshold 5.5 7 8.3 V
V(G2_GOOD) G2 Good rising threshold 5.5 7 8.3 V
GATE DRIVER OUTPUTS (G1PU, G1PD, G2)
I(G2) G2 Source Current 134 165 189 µA
I(G2) G2 Peak Sink Current 2 A
I(G1PU) Peak Source Current 1.69 A
I(G1PD) Peak Sink Current 2 A
SHORT CIRCUIT PROTECTION AND LOAD WAKE UP THRESHOLD (ISCP/LWU)
ISCP/LWU SCP/LWU Input Bias current 8.4 10 12.33 µA
V(SCP_HS) SCP threshold for HS configuration V(ISCP) = 1.405 V, CS_SEL = 0 V 277 300 332 mV
V(SCP/LWU) SCP/LWU threshold R(ISCP/LWU) =  140.5 kΩ 300 mV
R(ISCP/LWU) =  28 kΩ 60 75 90 mV
R(ISCP/LWU) =  10.5 kΩ 32 40 48 mV
R(ISCP/LWU) =  500 Ω 15 20 25 mV
R(ISCP/LWU) =  Open 757 mV
DELAY TIMER (TMR)
I(TMR_SRC_CB) TMR source current 67 87 104 µA
I(TMR_SRC_FLT) TMR source current  1.4 2.73 3.8 µA
I(TMR_SNK) TMR sink  current 2.17 2.8 3.4 µA
V(TMR_SC) 0.93 1.1 1.2 V
V(TMR_LOW) 0.15 0.21 0.25 V
N(A-R Count) 32
INPUT CONTROLS (INP, LPM), FAULT (FLT) & WAKE FLAG (WAKE)
R(FLT),  R(WAKE) FLT, WAKE Pull-down resistance 53 82 106.6 Ω
I(FLT),  I(WAKE) FLT, WAKE Input leakage current 0 V ≤ V(FLT) ≤ 20 V 410 nA
V(INP_H),  V(LPM_H) 2 V
V(INP_L), V(LPM_L) 0.8 V
I(INP), I(LPM)  INP, LPM Input leakage current 89 206 nA