The two primary considerations for selecting the value of the output capacitor are how the regulator responds to a large change in load current and the output voltage ripple. The third consideration is to ensure converter stability, which is typically met from the first two considerations. The output capacitance needs to be selected based on the most stringent of these criteria.

The desired response to a large change in the load current is the first criteria and is typically the most stringent. A regulator does not respond immediately to a large, fast increase or decrease in load current. The output capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop needs to sense the change in the output voltage then adjust the peak switch current in response to the change in load. The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically, the loop bandwidth is near f_SW/10. Equation 28 estimates the minimum output capacitance necessary, where I_STEP is the change in output current and V_TRANS is the allowable change in the output voltage.

For this example, the transient load response is specified as a 5% change in V_OUT1 for a load step of 3 A. Therefore, I_STEP1 is 3 A and V_TRANS1 is 50 mV. Using this target gives a minimum output capacitance of 95.5 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be considered for load step response. Similarly, I_STEP2 is 3 A and V_TRANS2 is 165 mV, which gives a minimum output capacitance of 28.9 μF.

In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp down after a load step down can be the limiting factor. Equation 29 estimates the minimum output capacitance necessary to limit the output voltage undershoot after a load step up. Equation 11 estimates the minimum output capacitance necessary to limit the change in the output voltage overshoot after a load step down. Using the selected 0.56-μH inductance gives a minimum capacitance of 4.6 μF for V_OUT1 to meet the undershoot requirement due to a load step-up. Using the selected 0.56-µH inductance gives a minimum capacitance of 50.4 µF for V_OUT1 to meet the overshoot requirement due to a load step down. Using the selected 1.2-μH inductance for V_OUT2 gives a minimum output capacitance of 3.8 μF and 9.9 μF to meet the undershoot and overshoot requirements, respectively.

Equation 31 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where f_sw is the switching frequency, V_RIPPLE1 is the maximum allowable steady-state output voltage ripple, and I_RIPPLE1 is the inductor ripple current. In this case, the target maximum steady-state output voltage ripple is 10 mV for V_OUT1. Under this requirement, Equation 31 yields 20.8 µF. Similarly, V_RIPPLE2 is the maximum allowable V_OUT2 steady-state output voltage ripple, and I_RIPPLE2 is the inductor ripple current for V_OUT2. For 33-mV steady-state output voltage ripple, Equation 31 yields 8.13 µF for V_OUT2.

Lastly, if an application does not have a stringent load transient response or output ripple requirement, a minimum amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp setting on the MODE pin. Equation 32 estimates the minimum capacitance needed for loop stability. Equation 32 sets the minimum amount of capacitance by keeping the LC frequency at a maximum of 1/30th the switching frequency. Equation 32 gives a minimum capacitance of 40.7 µF and 19 µF for V_OUT1 and V_OUT2, respectively.

Equation 33 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple specification and shows that the ESR must be less than 6 mΩ for V_OUT1. This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If the user is using non-ceramic capacitors as a starting point, the ESR must be below the values calculated in Equation 33 and Equation 15 to meet both the ripple and transient response requirements. For more accurate calculations or if you are using mixed output capacitors, the impedance of the output capacitors must be used to determine if the ripple and transient requirements can be met. Similary, Equation 33 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple specification. This shows the ESR must be less than 15.4 mΩ for V_OUT2. In this case, ceramic capacitors are used and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple.

Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data sheet specifies the RMS value of the maximum ripple current. Equation 35 can be used to calculate the RMS ripple current the output capacitor needs to support.

For this application, Equation 35 yields 0.481 A and 0.619 A, for V_OUT1 and V_OUT2, respectively. Ceramic capacitors typically have a ripple current rating much higher than this. Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors since they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website. For a V_OUT1 application example, three 100-μF, 6.3-V, X7S, 0805 ceramic capacitors, each with 2 mΩ of ESR, are used. With the three parallel capacitors, the estimated effective output capacitance after derating using the capacitor manufacturer’s website is 240 μF. This is well above the calculated minimum capacitance so this design is expected to meet the transient response requirement with added margin. Figure 8-13 shows the transient response and the output voltage stays within ±4%, below the ±5% target of ±50 mV for V_OUT1. For the V_OUT2 application example, two 100-μF, 6.3-V, X7S, 0805 ceramic capacitorsm each with 2 mΩ of ESRm are used. With the two parallel capacitors the estimated effective output capacitance after derating using the capacitor manufacturer’s website is 80 μF. Figure 8-14 shows the transient response and the output voltage stays within ±3%, below the ±5% target of ±165 mV for V_OUT2.