TI recommends to place all components as close as
possible to the IC. Specifically, the input capacitor placement must be closest
to the PVIN and PGND pins of the device.
The low side of the input and output capacitors must be connected directly to the PGND pin to avoid a ground potential shift.
Use the terminal of the input capacitor as the
common node for AVIN and PVIN, AGND, and PGND. It helps reduce the noise
coupling into the internal analog circuit blocks. Do not use a solid plane pour
to connect these nodes.
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
The sense trace connected to VOS pin is a signal trace. Special care should be taken to avoid noise being induced. By a direct routing, parasitic inductance can be kept small. Keep the trace away from SW nodes.
Refer to the Figure 11-1 for an example of component placement, routing, and thermal design.