SLVSCD6A December   2015  – January 2021 TPS62097


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommend Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 100% Duty Cycle Mode
      2. 8.3.2 Switch Current Limit and Hiccup Short Circuit Protection
      3. 8.3.3 Undervoltage Lockout (UVLO)
      4. 8.3.4 Thermal Shutdown
    4. 8.4 Device Function Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Power Save Mode and Forced PWM Mode (MODE)
      3. 8.4.3 Soft Start-up (SS/TR)
      4. 8.4.4 Voltage Tracking (SS/TR)
      5. 8.4.5 Power Good (PG)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 1.2-V Output Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Setting the Output Voltage
        2. Output Filter Design
        3. Inductor Selection
        4. Capacitor Selection
      3. 9.2.3 Application Performance Curves
      4. 9.2.4 Coincidental Voltage Tracking
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Performance Curve
      5. 9.2.5 Switching Frequency Selection
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Information
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Support Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Save Mode and Forced PWM Mode (MODE)

The MODE pin is a multi-functional pin that allows the device operation in forced PWM mode or PWM/PSM mode, and to select the PWM switching frequency.

Once the EN pin is pulled high, the IC enables internal circuit blocks and prepares to ramp the output up. The period between the rising edge of the EN pin and the beginning of the power stage switching is called the MODE detection time, typically 50 µs. During the MODE detection time period, shown in Figure 8-1, the PWM switching frequency and operating mode are set by the MODE pin status, as shown in Table 8-1.

The PWM switching frequency cannot be changed after the detection time period. Only when the device is set in PWM/PSM mode during the MODE detection time period (MODE = AGND), it is possible to switch between PWM/PSM and forced PWM operation modes by toggling the MODE pin with a GPIO pin of a microcontroller, for example. The other four MODE pin selections force the device in PWM mode only.

GUID-73CB8C44-E367-49F3-87E6-2FB94BF6AA5D-low.gifFigure 8-1 Power-up Sequence
Table 8-1 Switching Frequency and Mode Selection
1.508.2 kΩ ±5%NotON = 667 ns x VOUT / VINForced PWM
1.7518 kΩ ±5%NotON = 571 ns x VOUT / VINForced PWM
2.00AGNDYestON = 500 ns x VOUT / VINPWM/PSM and Forced PWM
2.2539 kΩ ±5%NotON = 444 ns x VOUT / VINForced PWM
2.5075 kΩ ±5% or OpenNotON = 400 ns x VOUT / VINForced PWM

Connecting the MODE pin to AGND with a resistor or leaving the MODE pin open forces the device into PWM mode for the whole load range. The device operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise sensitive applications. In forced PWM mode, the efficiency is lower than that of PSM at light load.

Connecting the MODE pin to the AGND pin enables Power Save Mode with an automatic transition between PWM and Power Save Mode. As the load current decreases and the inductor current becomes discontinuous, the device enters Power Save Mode operation automatically. In Power Save Mode, the switching frequency is reduced and estimated by Equation 2. In Power Save Mode, the output voltage rises slightly above the nominal output voltage, as shown in Figure 9-8. This effect is minimized by increasing the output capacitor.

Equation 2. GUID-EB7A0F7D-9F74-41FE-AF08-9BF69D107500-low.gif

When the device operates close to 100% duty cycle mode, the TPS62097 cannot enter Power Save Mode regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The device maintains output regulation in PWM mode.