SLVSFS6A May   2021  – September 2021 TPS629210-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Settable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Current Limit and Short Circuit Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 AEE (Automatic Efficiency Enhancement)
      3. 8.4.3 Power Save Mode Operation (Auto PFM/PWM)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Output Discharge Function
      6. 8.4.6 Starting into a Pre-Biased Load
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection
        1. 9.1.1.1 Programming the Output Voltage
        2. 9.1.1.2 Inductor Selection
        3. 9.1.1.3 Capacitor Selection
          1. 9.1.1.3.1 Output Capacitor
          2. 9.1.1.3.2 Input Capacitor
        4. 9.1.1.4 Output Filter and Loop Stability
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-20210614-CA0I-BLVS-FJJZ-RVBWBRZFP6V4-low.gif Figure 6-1 TPS629210-Q1 Pinout
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
FB/VSET 1 I Depending on device configuration (see Section 8.3.1)
  • FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
  • VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage according to Table 8-2.
PG 2 O Open-drain power-good output
VOS 3 I Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
SW 4 Switch pin of the converter. Connected to the internal power switches
GND 5 Ground pin
VIN 6 I Power supply input. Make sure the input capacitor is connected as close as possible between the VIN pin and GND.
EN 7 I Enable/Disable pin including a threshold comparator. Connect to logic low to disable the device. Pull high to enable the device. Do not leave this pin unconnected.
MODE/S-CONF 8 I Device Mode selection (Auto PFM/PWM or Forced PWM operation) and Smart-CONFIG pin. Connect a resistor to configure the device according to Table 8-1.