SLVSFS6A May   2021  – September 2021 TPS629210-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Settable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Current Limit and Short Circuit Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 AEE (Automatic Efficiency Enhancement)
      3. 8.4.3 Power Save Mode Operation (Auto PFM/PWM)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Output Discharge Function
      6. 8.4.6 Starting into a Pre-Biased Load
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection
        1. Programming the Output Voltage
        2. Inductor Selection
        3. Capacitor Selection
          1. Output Capacitor
          2. Input Capacitor
        4. Output Filter and Loop Stability
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Save Mode Operation (Auto PFM/PWM)

When the MODE/S-CONF pin is configured for Auto PFM/PWM mode, Power Save mode is allowed. The device operates in PWM mode as long the output current is higher than half the ripple current of the inductor. To maintain high efficiency at light loads, the device enters Power Save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the ripple current of the inductor. Power Save mode is entered seamlessly to ensure a high efficiency in light load operation. The device remains in Power Save mode as long as the inductor current is discontinuous.

In Power Save mode, the switching frequency decreases linearly with the load current maintaining high efficiency. The transition into and out of Power Save mode is seamless in both directions.

The TPS629210-Q1 adjusts the on time (TON) in Power Save mode, depending on the input voltage and the output voltage to maintain highest efficiency. The on time, in steady-state operation, can be estimated as:

With the MODE/S-CONF pin set to 1.0-MHz operation:

Equation 7. GUID-20210112-CA0I-2BBG-FRVV-6WRM687CFP7H-low.gif

With the MODE/S-CONF pin set to 2.5-MHz operation:

Equation 8. GUID-70F32A7D-8DBA-4C71-B90A-AB4A082502EF-low.gif

Using TON, the typical peak inductor current in Power Save mode is approximated by:

Equation 9. GUID-1B656C37-35A0-449B-B8E1-EE8E63D42731-low.gif

The output voltage ripple in Power Save mode is given by Equation 10:

Equation 10. GUID-2830085B-40AC-48CF-8325-E77571508CF3-low.gif

When VIN decreases to typically 15% above VOUT, the device does not enter Power Save mode, regardless of the load current. The device maintains output regulation in PWM mode.