SLVSFS6A May   2021  – September 2021 TPS629210-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Settable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Current Limit and Short Circuit Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 AEE (Automatic Efficiency Enhancement)
      3. 8.4.3 Power Save Mode Operation (Auto PFM/PWM)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Output Discharge Function
      6. 8.4.6 Starting into a Pre-Biased Load
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection
        1. 9.1.1.1 Programming the Output Voltage
        2. 9.1.1.2 Inductor Selection
        3. 9.1.1.3 Capacitor Selection
          1. 9.1.1.3.1 Output Capacitor
          2. 9.1.1.3.2 Input Capacitor
        4. 9.1.1.4 Output Filter and Loop Stability
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

VI = 3 V to 17 V, TJ = -40 °C to +150°C, Typical values at VI = 12.0 V and TA = 25 °C,unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Operating Quiescent Current (Power Save Mode) Iout = 0 mA, TJ = -40 °C to 150 °C, device not switching 4 µA
IQ;PWM Operating Quiescent Current (PWM Mode) VIN=12V, VOUT=1.2V; Iout = 0 mA, TJ = -40 °C to 150 °C, device switching 5 mA
ISD Shutdown current into VIN pin EN = 0 V, TJ = -40 °C to 85°C 0.3 6.5 µA
VUVLO Under Voltage Lock-Out VIN rising 2.85 2.925 3.0 V
Under Voltage Lock-Out VIN falling 2.7 2.775 2.85 V
VUVLO Under Voltage Lock-Out Hysteresis 230 mV
CONTROL & INTERFACE
ILKG EN Input leakage current EN = HIGH, TJ = -40°C to 125°C 10 100 nA
VIH;MODE High-Level Input Voltage at MODE/S-CONF Pin 1.0 V
VIL;MODE Low-level input voltage at MODE/S_CONF Pin 0.15 V
TSD Thermal Shutdown Threshold TJ rising 170 °C
Thermal Shutdown Hysteresis TJ falling 20
VIH High-level input voltage at EN-Pin 0.97 1.0 1.03 V
VIL Low-level input voltage at EN-Pin 0.87 0.9 0.93 V
VPG Power good threshold VFB rising, referenced to VFB nominal 94% 96% 98%
VFB falling, referenced to VFB nominal 89% 92% 96%
VPG_HYS Power good threshold hysteresis  hysteresis 4%
VPG,OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5 V, TJ = -40 °C to 125 °C 100 nA
tPG,DLY Power good delay time 32 µs
POWER SWITCHES
ILKG;SW Leakage current into SW-Pin EN = 0V, VSW = VOS = 5.5V,  TJ = -40°C to 125°C 2 7 µA
RDS;ON High-side FET on resistance 300
Low-side FET on resistance 100
ILIM High-side FET current limit 1.4 1.8 2.2 A
Low-side FET current limit 1.2 1.6 2.0 A
ILIM;SINK Low-side FET sink current limit 0.7 0.9 1.2 A
fSW Switching frequency 2.5-MHz selection 2.5 MHz
TON(MIN) Minimum On-time 50 ns
fSW Switching frequency 1.0-MHz selection 1.0 MHz
ILKG;VOS Leakage current into VOS-Pin 100 800 nA
OUTPUT
VO Output Voltage Regulation VSET Configuration selected, TJ = 25°C -0.5% +0.5%
VO Output Voltage Regulation VSET Configuration selected -1% +1%
VFB Feedback Regulation Voltage Adjustable Configuration selected 0.6 V
VFB Feedback Voltage Regulation FB-Option selected -1% +1%
IFB Input leakage current into FB pin Adjustable configuration, VFB = 0.6 V 1 100 nA
Tdelay Start-up delay time IO = 0 mA, time from EN rising edge until start switching, External FB Configuration selected 500 1500 µs
Start-up delay time IO = 0 mA, time from EN rising edge until start switching, VSET Configuration selected 750 1800 µs
TSS Soft-Start time IO = 0 mA after Tdelay, from 1st switching pulse until target VO 600 700 µs
RDISCH Active Discharge Resistance Discharge = ON - Option Selected, EN = LOW, 7.5 20