SLVSIH4 August   2025 TPS6521505-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1)
    9. 5.9  General Purpose LDOs (LDO2)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 and LDO2)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select Pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521505-Q1 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1 Design Procedure
        3. 7.2.3.3 LDO2 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.4 Application Curves

TPS6521505-Q1 Buck1 Ramp
VIN = 5.0V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth Iout = 1A COUT_total = 57μF
Figure 7-2 Buck1 Ramp
TPS6521505-Q1 Buck3 Ramp
VIN = 5.0V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth Iout = 1A COUT_total = 57μF
Figure 7-4 Buck3 Ramp
TPS6521505-Q1 LDO2 Fast Ramp
VIN = 5.0V VOUT = 3.3V TA = 25 °C
LDO mode / Fast ramp Iout = 300mA COUT_total = 10μF
Figure 7-6 LDO2 Fast Ramp
TPS6521505-Q1 Bucks Discharge
VIN = 5.0V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth no load COUT_total = 57μF
Figure 7-8 Bucks Discharge
TPS6521505-Q1 Configurable Power-up Sequence - Example
Slot# Duration Assigned Rail
0 1.5ms BUCK2
1 0ms
2 3 ms LDO1 / LDO2 / GPO1
3 1.5ms
4 1.5ms BUCK3
5 1.5ms BUCK1
6 1.5ms
7 10ms
8 1.5ms
9 10ms nRSTOUT
10-15 0ms
Figure 7-10 Configurable Power-up Sequence - Example
TPS6521505-Q1 Buck2 Ramp
VIN = 5.0V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth Iout = 1A COUT_total = 57μF
Figure 7-3 Buck2 Ramp
TPS6521505-Q1 LDO1 Ramp
VIN = 5.0V VOUT = 3.3V TA = 25 °C
LDO mode Iout = 400mA COUT_total = 10μF
Figure 7-5 LDO1 Ramp
TPS6521505-Q1 LDO2 Slow Ramp
VIN = 5.0V VOUT = 3.3V TA = 25 °C
LDO mode / Slow ramp Iout = 300mA COUT_total = 10μF
Figure 7-7 LDO2 Slow Ramp
TPS6521505-Q1 LDOs Discharge
VIN = 5.0V VOUT = 3.3V TA = 25 °C
LDO mode no load COUT_total = 2.2μF
Figure 7-9 LDOs Discharge
TPS6521505-Q1 Configurable Power-Down sequence - Example
Slot# Duration Assigned Rail
0 10ms nRSTOUT / BUCK3
1 0ms
2 10ms BUCK1 / LDO1 / LDO2 / GPO1
3 0ms
4 10ms BUCK2
5-15 0ms
Figure 7-11 Configurable Power-Down sequence - Example