SLVSIH4 August   2025 TPS6521505-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1)
    9. 5.9  General Purpose LDOs (LDO2)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 and LDO2)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select Pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521505-Q1 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1 Design Procedure
        3. 7.2.3.3 LDO2 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.13 Typical Characteristics

TPS6521505-Q1 Efficiency BUCK1
VIN = 5V VOUT = 1.8V TA = 25°C
Figure 5-1 Efficiency BUCK1
TPS6521505-Q1 BUCK1 Load-step Response - High Bandwidth, Forced PWM
VIN = 5.0V VOUT = 0.75V TA = 25 °C
IOUT = 100mA to 1.1 A to 100mA, trise=tfall=500ns COUT_total = 57μF
Figure 5-3 BUCK1 Load-step Response - High Bandwidth, Forced PWM
TPS6521505-Q1 BUCK3 Load-step Response - Low Bandwidth, Forced PWM
VIN = 5.0V VOUT = 1.2V TA = 25 °C
IOUT = 1mA to 1 A to 1mA, trise=tfall=1μs COUT_total = 57μF
Figure 5-5 BUCK3 Load-step Response - Low Bandwidth, Forced PWM
TPS6521505-Q1 LDO2 Load-step Response
VIN = 5V VOUT = 3.3V TA = 25 °C
IOUT = 60mA to 240mA to 60mA, trise=tfall=1μs COUT = 10μF
Figure 5-7 LDO2 Load-step Response
TPS6521505-Q1 Efficiency BUCK23
VIN = 5V VOUT = 1.8V TA = 25°C
Figure 5-2 Efficiency BUCK23
TPS6521505-Q1 BUCK2 Load-step Response - Low Bandwidth, Forced PWM
VIN = 5.0V VOUT = 3.3V TA = 25 °C
IOUT = 1mA to 1 A to 1mA, trise=tfall=1μs COUT_total = 57μF
Figure 5-4 BUCK2 Load-step Response - Low Bandwidth, Forced PWM
TPS6521505-Q1 LDO1 Load-step Response
VIN = 3.3V VOUT = 1.8V TA = 25 °C
IOUT = 80mA to 320mA to 80mA, trise=tfall=1μs COUT = 10μF
Figure 5-6 LDO1 Load-step Response