SLVSD86B december   2015  – may 2023 TPS65265

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Mix PGOOD, PG_DLY Functions
        1. 8.3.2.1 Programmable PGOOD DELAY
        2. 8.3.2.2 Relay Control
      3. 8.3.3  Enable and Adjusting UVLO
      4. 8.3.4  Soft-Start Time
      5. 8.3.5  Power-Up Sequencing
        1. 8.3.5.1 External Power Sequencing
        2. 8.3.5.2 Automatic Power Sequencing
      6. 8.3.6  V7V Low Dropout Regulator and Bootstrap
      7. 8.3.7  Out of Phase Operation
      8. 8.3.8  Output Overvoltage Protection (OVP)
      9. 8.3.9  PSM
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Overcurrent Protection
        1. 8.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 8.3.12 Adjustable Switching Frequency
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5.2 Automatic Power Sequencing

The TPS65265 starts with a predefined power-up and power-down sequence when MODE pin ties HIGH or ties to GND. As shown in Table 8-2, the sequence is determined by the different combinations of EN1 and EN2 status. EN3 is used to start and stop the converters. Figure 8-6 shows the power sequencing when MODE ties to GND, EN1, and EN2 are tied to HIGH.

An internal 3-µA pullup current source is connected to SEQ_DLY pin. The interval time between bucks can be programmed by connecting a capacitor between SEQ_DLY pin and ground. The interval time can be calculated with Equation 5.

Equation 5. GUID-139EF324-8B15-4E3B-AA50-7C954170FB94-low.gif
Equation 6. GUID-58FAE240-E563-420B-9E61-503C35A1DB45-low.gif

where

  • V1 = 0.75 V
  • V2 = 1.5 V
  • Ip = 3 µA
Table 8-2 Power Sequencing
MODEEN1EN2EN3START SEQUENCINGSHUTDOWN SEQUENCING
Automatic Power SequencingConnect to GNDHighHighUsed to start and stop bucks in sequencebuck1 → buck2 → buck3buck3 → buck2 → buck1
Connect to GNDLowHighbuck2 → buck1 → buck3buck3 → buck1 → buck2
Connect to GNDHighLowbuck2 → buck3 → buck1buck1 → buck3 → buck2
Connect to high or floatHighHighbuck1 → buck3 → buck2buck2 → buck3 → buck1
Connect to high or floatLowHighbuck3 → buck1 → buck2buck2 → buck1 → buck3
Connect to high or floatHighLowbuck3 → buck2 → buck1buck1 → buck2 → buck3
Connect to GNDLowLowReservedReservedReserved
Connect to high or floatLowLowReservedReservedReserved
Externally Controlled SequencingFloatingUsed to start and stop buck1Used to start and stop buck2Used to start and stop buck3xx
GUID-E887E8EB-D9CA-469E-8846-2D79992C0621-low.gifFigure 8-6 Automatic Power Sequencing