SLVSD86B december   2015  – may 2023 TPS65265

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Mix PGOOD, PG_DLY Functions
        1. 8.3.2.1 Programmable PGOOD DELAY
        2. 8.3.2.2 Relay Control
      3. 8.3.3  Enable and Adjusting UVLO
      4. 8.3.4  Soft-Start Time
      5. 8.3.5  Power-Up Sequencing
        1. 8.3.5.1 External Power Sequencing
        2. 8.3.5.2 Automatic Power Sequencing
      6. 8.3.6  V7V Low Dropout Regulator and Bootstrap
      7. 8.3.7  Out of Phase Operation
      8. 8.3.8  Output Overvoltage Protection (OVP)
      9. 8.3.9  PSM
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Overcurrent Protection
        1. 8.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 8.3.12 Adjustable Switching Frequency
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.4 Loop Compensation

The TPS65265 incorporates a peak current mode control scheme. The error amplifier is a trans-conductance amplifier with a gain of 350 µS. A typical type II compensation circuit adequately delivers a phase margin between 30 and 90 degrees. Cb adds a high frequency pole to attenuate high frequency noise when needed. To calculate the external compensation components, follow the following steps.

  1. Select switching frequency fsw that is appropriate for application depending on L and C sizes, output ripple, EMI, and so forth. Switching frequency between 600 kHz to 1 MHz gives best trade-off between performance and cost. To optimize efficiency, lower switching frequency is desired.
  2. Set up crossover frequency, ƒc, which is typically between 1/5 and 1/20 of ƒsw.
  3. RC can be determined by
    Equation 19. GUID-9F4FE1F5-9E1B-4EC1-A29D-3AAC0B9B2E22-low.gif

    where

    • Gm_EA is the error amplifier gain (350 µS).
    • Gm_PS is the power stage voltage to current conversion gain (12 A/V).
  4. Calculate CC by placing a compensation zero at or before the dominant pole ( GUID-31FA0C0B-CE5E-46BE-8BE3-77F65F118CF0-low.gif ).
    Equation 20. GUID-ADC6158A-982C-44CC-A5B1-809FDD96FB28-low.gif
  5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
    Equation 21. GUID-73ED3A90-8D0F-4CAB-8D92-D13FBF826384-low.gif
  6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly higher loop bandwidths and higher phase margins. If used, C1 is calculated from Equation 22.
    Equation 22. GUID-84A06A36-3588-49D1-B90E-7791E032EA22-low.gif
GUID-34940CFF-FC22-4C2F-B105-786F5F8C1A82-low.svgFigure 9-2 DC-DC Loop Compensation