SLVSCO4D July 2015 – February 2019 TPS65917-Q1
The GPC I2C interface (I2C1_SCL_SCK and I2C1_SDA_SDI) is dedicated to access the configuration registers of all the resources of the system.
The DVS I2C interface (I2C2_SCL_SCE and I2C_SDA_SDO) is dedicated to access the DVS registers independently from the GPC I2C.
The control interfaces comply with the HS-I2C specification and support the following features:
The following features are not supported:
I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus Specification and user manual, Rev 03, June 2007). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, the SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the start and stop of data transfers. A slave device receives data, transmits data, or both on the bus under control of the master device. The data transfer protocol for standard and fast modes is exactly the same. In this data sheet, these modes are referred to as F/S mode. The protocol for high-speed (HS) mode is different from F/S mode.