SLVSCO4D July 2015 – February 2019 TPS65917-Q1
The watchdog timer has two modes of operation: periodic mode and interrupt mode.
In periodic mode, an interrupt is generated with a regular period N, defined by the setting of WATCHDOG.TIMER. This interrupt is generated at the beginning of the period (when the watchdog internal counter equals 1). The IC initiates a shutdown at the end of the period (when the internal counter reaches N) only if the interrupt is not cleared within the defined time frame (0 to N). In this mode, when the interrupt is cleared, the internal counter is not reset. The counter continues counting until it reaches the maximum value (defined by the TIMER setting) and automatically rolls over to 0 to start a new counting period. Regardless of when the interrupt is cleared within a given period (N), the next interrupt is generated only when the ongoing period completes (reaches N). The internal watchdog counter is initialized and kept at 0 as long as the RESET_OUT pin is low. The watchdog counter begins counting when the RESET_OUT pin is released.
In interrupt mode, any interrupt source resets the watchdog counter and starts the counting. If the sources of the interrupts are not cleared (meaning the INT line is released) before the end of the predefined period, N (set by WATCHDOG.TIMER setting), then the device initiates a shutdown. If the sources of the interrupts are cleared within the predefined period, then the watchdog counter is discarded (dc) and no shutdown sequence is initiated.
By default, the watchdog is disabled. The watchdog can be enabled by setting the ENABLE bit of the WATCHDOG register to 1, and this selection is write protected by setting the LOCK bit to 1. Reset of the device returns these bits to default values.